Parallel block-layered nonbinary QC-LDPC decoding on GPU. - Huyen Thi Pham; Sabooh Ajaz; Hanho Lee (SiPS, 2015)

Low latency check node unit architecture for nonbinary LDPC decoding. - Huyen Thi Pham; Hanho Lee (APCCAS, 2016)

High-throughput partial-parallel block-layered decoding architecture for nonbinary LDPC codes. - Huyen Thi Pham; Sabooh Ajaz; Hanho Lee (Integr., 2017)

Two-Extra-Column Trellis Min-Max Decoder Architecture for Nonbinary LDPC Codes. - Huyen Thi Pham; Hanho Lee (IEEE Trans. Very Large Scale Integr. Syst., 2017)

Basic-Set Trellis Min-Max Decoder Architecture for Nonbinary LDPC Codes With High-Order Galois Fields. - Huyen Thi Pham; Hanho Lee (IEEE Trans. Very Large Scale Integr. Syst., 2018)