Impact of guard ring layout on the stacked low-voltage PMOS for high-voltage ESD protection. - Seian-Feng Liao; Kai-Neng Tang; Ming-Dou Ker; Jia-Rong Yeh; Hwa-Chyi Chiou; Yeh-Jen Huang; Chun-Chien Tsai; Yeh-Ning Jou; Geeng-Lih Lin (ECCTD, 2015)

Analyzing Gate-Driven Circuit Parameters for Adding ESD Performances. - Shao-Chang Huang; Chih-Cherng Liao; Hsien-Feng Liao; Shou-Peng Weng; Karuna Nidhi; Yu-Kai Wang; Yi-Jen Chen; Hwa-Chyi Chiou; Yeh-Ning Jou; Jian-Hsing Lee (ICCE-TW, 2019)