Analog CMOS Implementation of Neural Network for Adaptive Signal Processing. - Hwa-Joon Oh; Fathi M. A. Salam (ISCAS, 1994)

Real-time tracking control using modular neural chips with on-chip learning. - Fathi M. A. Salam; Hwa-Joon Oh (ICNN, 1996)

The Vector Floating-Point Unit in a Synergistic Processor Element of a CELL Processor. - Silvia M. Müller; Christian Jacobi 002; Hwa-Joon Oh; Kevin D. Tran; Scott R. Cottier; Brad W. Michael; Hiroo Nishikawa; Yonetaro Totsuka; Tatsuya Namatame; Naoka Yano; Takashi Machida; Sang H. Dhong (IEEE Symposium on Computer Arithmetic, 2005)

The circuit design of the synergistic processor element of a CELL processor. - Osamu Takahashi; Russ Cook; Scott R. Cottier; Sang H. Dhong; Brian K. Flachs; Koji Hirairi; Atsushi Kawasumi; Hiroaki Murakami; Hiromi Noro; Hwa-Joon Oh; S. Onish; Juergen Pille; et al. (ICCAD, 2005)

The microarchitecture of the synergistic processor for a cell processor. - Brian K. Flachs; Shigehiro Asano; Sang H. Dhong; H. Peter Hofstee; Gilles Gervais; Roy Kim; Tien Le; Peichun Liu; Jens Leenstra; John S. Liberty; Brad W. Michael; Hwa-Joon Oh; et al. (IEEE J. Solid State Circuits, 2006)

A fully pipelined single-precision floating-point unit in the synergistic processor element of a CELL processor. - Hwa-Joon Oh; Silvia M. Müller; Christian Jacobi 002; Kevin D. Tran; Scott R. Cottier; Brad W. Michael; Hiroo Nishikawa; Yonetaro Totsuka; Tatsuya Namatame; Naoka Yano; Takashi Machida; Sang H. Dhong (IEEE J. Solid State Circuits, 2006)

Microarchitecture and implementation of the synergistic processor in 65-nm and 90-nm SOI. - Brian K. Flachs; Shigehiro Asano; Sang H. Dhong; H. Peter Hofstee; Gilles Gervais; Roy Kim; Tien Le; Peichun Liu; Jens Leenstra; John S. Liberty; Brad W. Michael; Hwa-Joon Oh; et al. (IBM J. Res. Dev., 2007)