8.7 A 0.0047mm2 highly synthesizable TDC- and DCO-less fractional-N PLL with a seamless lock range of fREF to 1GHz. - Hwasuk Cho; Kihwan Seong; Kwang-Hee Choi; Jin-Hyeok Choi; Byungsub Kim; Hong-June Park; Jae-Yoon Sim (ISSCC, 2017)

A Low-Power Wide Dynamic-Range Current Readout Circuit for Ion-Sensitive FET Sensors. - Hyunwoo Son; Hwasuk Cho; Jahyun Koo 001; Youngwoo Ji; Byungsub Kim; Hong-June Park; Jae-Yoon Sim (IEEE Trans. Biomed. Circuits Syst., 2017)

A 250-µW 2.4-GHz Fast-Lock Fractional-N Frequency Generation for Ultralow-Power Applications. - Seunghwan Hong; Shinwoong Kim; Seungnam Choi; Hwasuk Cho; Jaehyeong Hong; Young Hun Seo; Byungsub Kim; Hong-June Park; Jae-Yoon Sim (IEEE Trans. Circuits Syst. II Express Briefs, 2017)

A low-power wide dynamic-range current readout circuit for biosensors. - Hyunwoo Son; Hwasuk Cho; Jahyun Koo 001; Youngwoo Ji; Byungsub Kim; Hong-June Park; Jae-Yoon Sim (ASP-DAC, 2018)

A 0.3-to-1.2V frequency-scalable fractional-N ADPLL with a speculative dual-referenced interpolating TDC. - Minseob Lee; Shinwoong Kim; Hwasuk Cho; Jahyun Koo 001; Kwang-Hee Choi; Jin-Hyeok Choi; Byungsub Kim; Hong-June Park; Jae-Yoon Sim (ISSCC, 2018)

An On-Chip Learning Neuromorphic Autoencoder With Current-Mode Transposable Memory Read and Virtual Lookup Table. - Hwasuk Cho; Hyunwoo Son; Kihwan Seong; Byungsub Kim; Hong-June Park; Jae-Yoon Sim (IEEE Trans. Biomed. Circuits Syst., 2018)

A Multilayer-Learning Current-Mode Neuromorphic System With Analog-Error Compensation. - Hyunwoo Son; Hwasuk Cho; Jungho Lee; Seongun Bae; Byungsub Kim; Hong-June Park; Jae-Yoon Sim (IEEE Trans. Biomed. Circuits Syst., 2019)

A 1.8 Gb/s/pin 16Tb NAND Flash Memory Multi-Chip Package with F-Chip of Toggle 4.0 Specification for High Performance and High Capacity Storage Systems. - Jang-Woo Lee; Dae-Hoon Na; Anil Kavala; Hwasuk Cho; Junha Lee; Manjae Yang; Eunjin Song; Tongsung Kim; Seon-Kyoo Lee; Dong-Su Jang; Byung-Kwan Chun; Youngmin Jo; et al. (VLSI Circuits, 2020)

A 1.8-Gb/s/Pin 16-Tb NAND Flash Memory Multi-Chip Package With F-Chip for High-Performance and High-Capacity Storage. - Dae-Hoon Na; Jang-Woo Lee; Seon-Kyoo Lee; Hwasuk Cho; Junha Lee; Manjae Yang; Eunjin Song; Anil Kavala; Tongsung Kim; Dong-Su Jang; Youngmin Jo; Ji-Yeon Shin; et al. (IEEE J. Solid State Circuits, 2021)

A 26GHz Fractional-N Digital Frequency Synthesizer Leveraging Noise Profiles of Three Functional Stages. - Seongun Bae; Minseob Lee; Hwasuk Cho; Jae-Yoon Sim (IEEE Trans. Circuits Syst. II Express Briefs, 2021)