Row-Streaming Dataflow Using a Chaining Buffer and Systolic Array+ Structure. - Hweesoo Kim; Sunjung Lee; Jaewan Choi; Jung Ho Ahn (IEEE Comput. Archit. Lett., 2021)

An FPGA-based RNN-T Inference Accelerator with PIM-HBM. - Shinhaeng Kang; Sukhan Lee 002; Byeongho Kim; Hweesoo Kim; Kyomin Sohn; Nam Sung Kim; Eojin Lee (FPGA, 2022)

MVP: An Efficient CNN Accelerator with Matrix, Vector, and Processing-Near-Memory Units. - Sunjung Lee; Jaewan Choi; Wonkyung Jung; Byeongho Kim; Jaehyun Park 006; Hweesoo Kim; Jung Ho Ahn (ACM Trans. Design Autom. Electr. Syst., 2022)