A 10-BIT 100MS/s pipelined ADC IN 0.18μm CMOS technology. - Hwei-Yu Lee; Shen-Iuan Liu (SoCC, 2007)

A 7-BIT 400MS/s sub-ranging flash ADC in 0.18um CMOS. - Hwei-Yu Lee; I-Hsin Wang; Shen-Iuan Liu (SoCC, 2007)

A 140MS/s 10-bit Pipelined ADC with a Folded S/H Stage. - Hwei-Yu Lee; Shen-Iuan Liu (ISCAS, 2009)

An 8-bit 20-MS/s ZCBC Time-Domain Analog-to-Digital Data Converter. - I-Hsin Wang; Hwei-Yu Lee; Shen-Iuan Liu (IEEE Trans. Circuits Syst. II Express Briefs, 2009)

Zero-crossing-based 8-bit 100 MS/s pipelined analogue-to-digital converter with offset compensation. - Hwei-Yu Lee (IET Circuits Devices Syst., 2011)