Modeling of nano-scale PLL using Verilog HDL. - Hye-Hyun Lee; Yeon-Seob Song; Kang-Yoon Lee (ICTC, 2022)

Design of a Fault Detection Circuit for One-Time Programmable Memories for Reducing Time. - Hye-Hyun Lee; Kang-Yoon Lee (ICUFN, 2023)

Hardware Honeypot: Setting Sequential Reverse Engineering on a Wrong Track. - Michaela Brunner; Hye-Hyun Lee; Alexander Hepp; Johanna Baehr 001; Georg Sigl (DDECS, 2024)