A high-gain wide-input-range time amplifier with an open-loop architecture and a gain equal to current bias ratio. - Hye-Jung Kwon; Jae-Seung Lee; Jae-Yoon Sim; Hong-June Park (A-SSCC, 2011)

A 0.4 V driving multi-touch capacitive sensor with the driving signal frequency set to (n+0.5) times the inverse of the LCD VCOM noise period. - Jae-Seung Lee; Dong-Hee Yeo; Sang-Soo Lee; Hye-Jung Kwon; Jae-Yoon Sim; Byungsub Kim; Hong-June Park (ISCAS, 2014)

Analysis of an Open-Loop Time Amplifier With a Time Gain Determined by the Ratio of Bias Current. - Hye-Jung Kwon; Jae-Seung Lee; Byungsub Kim; Jae-Yoon Sim; Hong-June Park (IEEE Trans. Circuits Syst. II Express Briefs, 2014)

23.4 An extremely low-standby-power 3.733Gb/s/pin 2Gb LPDDR4 SDRAM for wearable devices. - Hye-Jung Kwon; Eunsung Seo; ChangYong Lee; Young-Hun Seo; Gong-Heum Han; Hye-Ran Kim; Jong-Ho Lee; Min-Su Jang; Sung-Geun Do; Seung-Hyun Cho; Jae-Koo Park; Su-Yeon Doo; et al. (ISSCC, 2017)

A 16Gb 18Gb/S/pin GDDR6 DRAM with per-bit trainable single-ended DFE and PLL-less clocking. - Young-Ju Kim 001; Hye-Jung Kwon; Su-Yeon Doo; Yoon-Joo Eom; Young-Sik Kim; Min-Su Ahn; Yong-Hun Kim; Sang-Hoon Jung; Sung-Geun Do; Chang-Yong Lee; Jae-Sung Kim; Dong-Seok Kang; et al. (ISSCC, 2018)

A 16-Gb, 18-Gb/s/pin GDDR6 DRAM With Per-Bit Trainable Single-Ended DFE and PLL-Less Clocking. - Young-Ju Kim 001; Hye-Jung Kwon; Su-Yeon Doo; Min-Su Ahn; Yong-Hun Kim; Yong Jae Lee; Dong-Seok Kang; Sung-Geun Do; Chang-Yong Lee; Gun-hee Cho; Jae-Koo Park; Jae-Sung Kim; et al. (IEEE J. Solid State Circuits, 2019)

A Duo-Binary Transceiver With Time-Based Receiver and Voltage-Mode Time-Interleaved Mixing Transmitter for DRAM Interface. - Min-Kyun Chae; Hye-Jung Kwon; Seung-Jun Bae; Nam-Jong Kim; Hong-June Park (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

A 16Gb 27Gb/s/pin T-coil based GDDR6 DRAM with Merged-MUX TX, Optimized WCK Operation, and Alternative-Data-Bus. - Daewoong Lee; Hye-Jung Kwon; Daehyun Kwon; Jaehyeok Baek; Chulhee Cho; Sanghoon Kim; Donggun An; Chulsoon Chang; Unhak Lim; Jiyeon Im; Wonju Sung; Hye-Ran Kim; et al. (ISSCC, 2022)

A 16-Gb T-Coil-Based GDDR6 DRAM With Merged-MUX TX, Optimized WCK Operation, and Alternative-Data-Bus Achieving 27-Gb/s/Pin in NRZ. - Daewoong Lee; Jaehyeok Baek; Hye-Jung Kwon; Daehyun Kwon; Chulhee Cho; Sang-Hoon Kim; Donggun An; Chulsoon Chang; Unhak Lim; Jiyeon Im; Wonju Sung; Hye-Ran Kim; et al. (IEEE J. Solid State Circuits, 2023)