An advanced bit-line clamping scheme in magnetic RAM for wide sensing margin. - Jong-Chul Lim; Hye-Seung Yu; Jae-Suk Choi; Soo-Won Kim (ASP-DAC, 2005)

Design of non-contact 2Gb/s I/O test methods for high bandwidth memory (HBM). - Hyunui Lee; Sukyong Kang; Hye-Seung Yu; Won-Joo Yun; Jae-Hun Jung; Sungoh Ahn; Wang-Soo Kim; Beomyong Kil; Yoo-Chang Sung; Sang-Hoon Shin; Yong-Sik Park; Yong-Hwan Kim; et al. (A-SSCC, 2016)

18.2 A 1.2V 20nm 307GB/s HBM DRAM with at-speed wafer-level I/O test scheme and adaptive refresh considering temperature distribution. - Kyomin Sohn; Won-Joo Yun; Reum Oh; Chi-Sung Oh; Seong-Young Seo; Min-Sang Park; Dong-Hak Shin; Won-Chang Jung; Sang-Hoon Shin; Je-Min Ryu; Hye-Seung Yu; Jae-Hun Jung; et al. (ISSCC, 2016)

A 1.2 V 20 nm 307 GB/s HBM DRAM With At-Speed Wafer-Level IO Test Scheme and Adaptive Refresh Considering Temperature Distribution. - Kyomin Sohn; Won-Joo Yun; Reum Oh; Chi-Sung Oh; Seong-Young Seo; Min-Sang Park; Dong-Hak Shin; Won-Chang Jung; Sang-Hoon Shin; Je-Min Ryu; Hye-Seung Yu; Jae-Hun Jung; et al. (IEEE J. Solid State Circuits, 2017)

Industry's First 7.2 Gbps 512GB DDR5 Module. - Sung Joo Park; Jonghoon J. Kim; Kun Joo; Young-Ho Lee; Kyoungsun Kim; Young-Tae Kim; Woo-Jin Na; IkJoon Choi; Hye-Seung Yu; Wonyoung Kim; Ju-Yeon Jung; Jaejun Lee; et al. (HCS, 2021)

A 1.1V 6.4Gb/s/pin 24-Gb DDR5 SDRAM with a Highly-Accurate Duty Corrector and NBTI-Tolerant DLL. - Daehyun Kwon; Heon Su Jeong; Jaemin Choi; Wijong Kim; Jae Woong Kim; Junsub Yoon; Jungmin Choi; Sanguk Lee; Hyunsub Norbert Rie; Jin-Il Lee; Jongbum Lee; Taeseong Jang; et al. (ISSCC, 2023)