A Data-Pattern-Tolerant Adaptive Equalizer Using the Spectrum Balancing Method. - Hye-Yoon Joo; Lee-Sup Kim (IEEE Trans. Circuits Syst. II Express Briefs, 2010)

18.1 A 20nm 9Gb/s/pin 8Gb GDDR5 DRAM with an NBTI monitor, jitter reduction techniques and improved power distribution. - Hye-Yoon Joo; Seung-Jun Bae; Young-Soo Sohn; Young-Sik Kim; Kyung-Soo Ha; Min-Su Ahn; Young-Ju Kim 001; Yong-Jun Kim; Ju-Hwan Kim; Won-Jun Choi; Chang-Ho Shin; Soo Hwan Kim; et al. (ISSCC, 2016)

A Maximum-Eye-Tracking CDR with Biased Data-Level and Eye Slope Detector for Optimal Timing Adaptation. - Hye-Yoon Joo; Deog-Kyoon Jeong (A-SSCC, 2019)

A 0.1-pJ/b/dB 28-Gb/s Maximum-Eye Tracking, Weight-Adjusting MM CDR and Adaptive DFE with Single Shared Error Sampler. - Moon-Chul Choi; Han-Gon Ko; Jonghyun Oh; Hye-Yoon Joo; Kwangho Lee; Deog-Kyoon Jeong (VLSI Circuits, 2020)

A Maximum-Eye-Tracking CDR With Biased Data-Level and Eye Slope Detector for Near-Optimal Timing Adaptation. - Hye-Yoon Joo; Jinhyung Lee; Haram Ju; Han-Gon Ko; Jungmin Yoon; Byungjun Kang; Deog-Kyoon Jeong (IEEE Trans. Very Large Scale Integr. Syst., 2020)

A 16Gb 9.5Gb/S/pin LPDDR5X SDRAM With Low-Power Schemes Exploiting Dynamic Voltage-Frequency Scaling and Offset-Calibrated Readout Sense Amplifiers in a Fourth Generation 10nm DRAM Process. - Dae-Hyun Kim 003; Byungkyu Song; Hyun-A. Ahn; Woongjoon Ko; Sung-Geun Do; Seokjin Cho; Kihan Kim; Seung-Hoon Oh; Hye-Yoon Joo; Geuntae Park; Jin-Hun Jang; Yong-Hun Kim; et al. (ISSCC, 2022)