Smart non-default routing for clock power reduction. - Andrew B. Kahng; Seokhyeong Kang; Hyein Lee 001 (DAC, 2013)

High-performance gate sizing with a signoff timer. - Andrew B. Kahng; Seokhyeong Kang; Hyein Lee 001; Igor L. Markov; Pankit Thapar (ICCAD, 2013)

Learning-based approximation of interconnect delay and slew in signoff timing tools. - Andrew B. Kahng; Seokhyeong Kang; Hyein Lee 001; Siddhartha Nath; Jyoti Wadhwani (SLIP, 2013)

Minimum implant area-aware gate sizing and placement. - Andrew B. Kahng; Hyein Lee 001 (ACM Great Lakes Symposium on VLSI, 2014)

Horizontal benchmark extension for improved assessment of physical CAD research. - Andrew B. Kahng; Hyein Lee 001; Jiajia Li 002 (ACM Great Lakes Symposium on VLSI, 2014)

Timing margin recovery with flexible flip-flop timing model. - Andrew B. Kahng; Hyein Lee 001 (ISQED, 2014)

Evaluation of BEOL design rule impacts using an optimal ILP-based detailed router. - Kwangsoo Han; Andrew B. Kahng; Hyein Lee 001 (DAC, 2015)

Scalable Detailed Placement Legalization for Complex Sub-14nm Constraints. - Kwangsoo Han; Andrew B. Kahng; Hyein Lee 001 (ICCAD, 2015)

Measuring progress and value of IC implementation technology. - Andrew B. Kahng; Hyein Lee 001; Jiajia Li 002 (ICCAD, 2016)

Vertical M1 Routing-Aware Detailed Placement for Congestion and Wirelength Reduction in Sub-10nm Nodes. - Peter Debacker; Kwangsoo Han; Andrew B. Kahng; Hyein Lee 001; Praveen Raghavan; Lutong Wang (DAC, 2017)

Optimal multi-row detailed placement for yield and model-hardware correlation improvements in sub-10nm VLSI. - Changho Han; Kwangsoo Han; Andrew B. Kahng; Hyein Lee 001; Lutong Wang; Bangqi Xu (ICCAD, 2017)

Performance- and energy-aware optimization of BEOL interconnect stack geometry in advanced technology nodes. - Kwangsoo Han; Andrew B. Kahng; Hyein Lee 001; Lutong Wang (ISQED, 2017)

MILP-Based Optimization of 2-D Block Masks for Timing-Aware Dummy Segment Removal in Self-Aligned Multiple Patterning Layouts. - Peter Debacker; Kwangsoo Han; Andrew B. Kahng; Hyein Lee 001; Praveen Raghavan; Lutong Wang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017)

PROBE: A Placement, Routing, Back-End-of-Line Measurement Utility. - Alex Kahng; Andrew B. Kahng; Hyein Lee 001; Jiajia Li 002 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018)

Physical Design and Technology Optimizations for Advanced VLSI Manufacturing - Hyein Lee 001 (2018)

Enhancing sensitivity-based power reduction for an industry IC design context. - Hamed Fatemi; Andrew B. Kahng; Hyein Lee 001; Jiajia Li 002; José Pineda de Gyvez (Integr., 2019)

Heuristic Methods for Fine-Grain Exploitation of FDSOI. - Hamed Fatemi; Andrew B. Kahng; Hyein Lee 001; José Pineda de Gyvez (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)