A CNN Inference Accelerator on FPGA With Compression and Layer-Chaining Techniques for Style Transfer Applications. - Suchang Kim; Boseon Jang; Jaeyoung Lee 004; Hyungjoon Bae 001; Hyejung Jang; In-Cheol Park (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

Area-Efficient QC-LDPC Decoding Architecture With Thermometer Code-Based Sorting and Relative Quasi-Cyclic Shifting. - Boseon Jang; Hyejung Jang; Sungho Kim; Kangjoon Choi; In-Cheol Park (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)