Multi-Slew-Rate Output Driver and Optimized Impedance-Calibration Circuit for 66nm 3.0Gb/s/pin DRAM Interface. - Dong-Uk Lee; Shin-Deok Kang; Nak-Kyu Park; Hyun-Woo Lee; Young-Kyoung Choi; Jung-Woo Lee; Seung-Wook Kwack; Hyeong-Ouk Lee; Won-Joo Yun; Sang-Hoon Shin; Kwan-Weon Kim; Young-Jung Choi; et al. (ISSCC, 2008)

A 0.1-to-1.5GHz 4.2mW All-Digital DLL with Dual Duty-Cycle Correction Circuit and Update Gear Circuit for DRAM in 66nm CMOS Technology. - Won-Joo Yun; Hyun-Woo Lee; Dongsuk Shin; Shin-Deok Kang; Ji-Yeon Yang; Hyeng-Ouk Lee; Dong-Uk Lee; Sujeong Sim; Young-Ju Kim 001; Won-Jun Choi; Keun-Soo Song; Sang-Hoon Shin; et al. (ISSCC, 2008)

A 1.6V 3.3Gb/s GDDR3 DRAM with dual-mode phase- and delay-locked loop using power-noise management with unregulated power supply in 54nm CMOS. - Hyun-Woo Lee; Won-Joo Yun; Young-Kyoung Choi; Hyang-Hwa Choi; Jong-Jin Lee; Ki-Han Kim; Shin-Deok Kang; Ji-Yeon Yang; Jae-Suck Kang; Hyeng-Ouk Lee; Dong-Uk Lee; Sujeong Sim; et al. (ISSCC, 2009)