A 7b 1GS/s 7.2mW nonbinary 2b/cycle SAR ADC with register-to-DAC direct control. - Hyeok-Ki Hong; Wan Kim; Sun-Jae Park; Michael Choi; Ho-Jin Park; Seung-Tak Ryu (CICC, 2012)

An 8.6 ENOB 900MS/s time-interleaved 2b/cycle SAR ADC with a 1b/cycle reconfiguration for resolution enhancement. - Hyeok-Ki Hong; Hyun-Wook Kang; Barosaim Sung; Choong-Hoon Lee; Michael Choi; Ho-Jin Park; Seung-Tak Ryu (ISSCC, 2013)

26.7 A 2.6b/cycle-architecture-based 10b 1 JGS/s 15.4mW 4×-time-interleaved SAR ADC with a multistep hardware-retirement technique. - Hyeok-Ki Hong; Hyun-Wook Kang; Dong-Shin Jo; Dong-Suk Lee; Yong-Sang You; Yong-Hee Lee; Ho-Jin Park; Seung-Tak Ryu (ISSCC, 2015)

Ternary-level thermometer C-DAC switching scheme for flash-assisted SAR ADCs. - Hyun-Wook Kang; Hyeok-Ki Hong; Sanghoon Park; Ki-Jin Kim; Kwang-Ho Ahn; Seung-Tak Ryu (IEICE Electron. Express, 2015)

A Decision-Error-Tolerant 45 nm CMOS 7b 1 GS/s Nonbinary 2b/Cycle SAR ADC. - Hyeok-Ki Hong; Wan Kim; Hyun-Wook Kang; Sun-Jae Park; Michael Choi; Ho-Jin Park; Seung-Tak Ryu (IEEE J. Solid State Circuits, 2015)

A 0.6 V 12 b 10 MS/s Low-Noise Asynchronous SAR-Assisted Time-Interleaved SAR (SATI-SAR) ADC. - Wan Kim; Hyeok-Ki Hong; Yi-Ju Roh; Hyun-Wook Kang; Sun-Il Hwang; Dong-Shin Jo; Dong-Jin Chang; Min-Jae Seo; Seung-Tak Ryu (IEEE J. Solid State Circuits, 2016)

A Sign-Equality-Based Background Timing-Mismatch Calibration Algorithm for Time-Interleaved ADCs. - Hyun-Wook Kang; Hyeok-Ki Hong; Sanghoon Park; Ki-Jin Kim; Kwang-Ho Ahn; Seung-Tak Ryu (IEEE Trans. Circuits Syst. II Express Briefs, 2016)

Normalized-Full-Scale-Referencing Digital-Domain Linearity Calibration for SAR ADC. - Dong-Jin Chang; Wan Kim; Min-Jae Seo; Hyeok-Ki Hong; Seung-Tak Ryu (IEEE Trans. Circuits Syst. I Regul. Pap., 2017)

A Time-Interleaved 12-b 270-MS/s SAR ADC With Virtual-Timing-Reference Timing-Skew Calibration Scheme. - Hyun-Wook Kang; Hyeok-Ki Hong; Wan Kim; Seung-Tak Ryu (IEEE J. Solid State Circuits, 2018)

A 65 nm 0.08-to-680 MHz Low-Power Synthesizable MDLL With Nested-Delay Cell and Background Static Phase Offset Calibration. - Dong-Jin Chang; Min-Jae Seo; Hyeok-Ki Hong; Seung-Tak Ryu (IEEE Trans. Circuits Syst. II Express Briefs, 2018)

A 62dB-SNDR 40.2μW 10MS/s ADC for Power Efficient IoT and Biomedical Read-Out Systems. - Hyeok-Ki Hong; Hyun-Wook Kang; Che-Heung Kim (ISCAS, 2020)