Packet Routing in Networks with Long Wires. - Ronald I. Greenberg; Hyeong-Cheol Oh (J. Parallel Distributed Comput., 1995)

Universal Wormhole Routing. - Ronald I. Greenberg; Hyeong-Cheol Oh (IEEE Trans. Parallel Distributed Syst., 1997)

Efficient Hardware Multiplicative Inverters. - Hyun-Gyu Kim; Hyeong-Cheol Oh (ICISC, 2002)

A DSP-Enhanced 32-Bit Embedded Microprocessor. - Hyun-Gyu Kim; Hyeong-Cheol Oh (EUC, 2005)

A Low-Power DSP-Enhanced 32-Bit EISC Processor. - Hyun-Gyu Kim; Hyeong-Cheol Oh (HiPEAC, 2005)

An Accelerator for Rendering 2D Vector Graphics. - Sang-Woo Seo; Yong-Luo Shen; Sang-Chol Lee; Jong-Sung Lee; Hyeong-Cheol Oh (CGVR, 2010)

Accelerating Java Interpretation in Low-Cost Embedded Processors. - Taek-Kyu Kim; Jong-Sung Lee; Hyeong-Cheol Oh (J. Circuits Syst. Comput., 2010)

Scanline-based rendering of 2D vector graphics. - Sang-Woo Seo; Yong-Luo Shen; Kwan-Young Kim; Hyeong-Cheol Oh (IEICE Electron. Express, 2011)

Design of an OpenVG Hardware Rendering Engine. - Yong-Luo Shen; Seok-Jae Kim; Sang-Woo Seo; Hyun-Goo Lee; Hyeong-Cheol Oh (IEICE Trans. Inf. Syst., 2011)

Handling Edge Lists in 2D Vector Graphics Hardware. - Sang-Woo Seo; Yong-Luo Shen; Kwan-Young Kim; Hyeong-Cheol Oh (J. Circuits Syst. Comput., 2012)

Pipelined implementation of AI-based Loeffler DCT. - Yong-Luo Shen; Hyeong-Cheol Oh (IEICE Electron. Express, 2013)

Design of a Loeffler DCT using Xilinx Vivado HLS (Abstract Only). - Seung Yeol Baik; Seokjin Jeong; Hyeong-Cheol Oh (FPGA, 2015)

Loeffler DCT accelerator for small portable devices. - Yong-Luo Shen; Seokjin Jung; Hyeong-Cheol Oh (IEICE Electron. Express, 2015)

Pipelined Squarer for Unsigned Integers of Up to 12 Bits. - Seongjin Choi; Hyeong-Cheol Oh (IEICE Trans. Inf. Syst., 2018)

LSTM-Guided Coaching Assistant for Table Tennis Practice. - Se-Min Lim; Hyeong-Cheol Oh; Jaein Kim; Juwon Lee; Jooyoung Park (Sensors, 2018)

Low-Cost Method for Recognizing Table Tennis Activity. - Se-Min Lim; Jooyoung Park; Hyeong-Cheol Oh (IEICE Trans. Inf. Syst., 2019)