FIR Filter Synthesis Algorithms for Minimizing the Delay and the Number of Adders. - Hyeong-Ju Kang; Hansoo Kim; In-Cheol Park (ICCAD, 2000)

Digital Filter Synthesis Based on Minimal Signed Digit Representation. - In-Cheol Park; Hyeong-Ju Kang (DAC, 2001)

Multiplier-less IIR filter synthesis algorithms to trade-off the delay and the number of adders. - Hyeong-Ju Kang; In-Cheol Park (ISCAS (2), 2001)

A high-speed and low-latency Reed-Solomon decoder based on a dual-line structure. - Hyeong-Ju Kang; In-Cheol Park (ICASSP, 2002)

Digital filter synthesis based on an algorithm to generate all minimal signed digit representations. - In-Cheol Park; Hyeong-Ju Kang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002)

Pairing and ordering to reduce hardware complexity in cascade form filter design. - Hyeong-Ju Kang; In-Cheol Park (ISCAS (4), 2003)

A 24-bit floating-point audio DSP controller supporting fast exponentiation. - Sung-Won Lee 005; Hyeong-Ju Kang; In-Cheol Park (ISCAS (2), 2003)

A scalable SIMD digital signal processor for high-quality multifunctional printer systems. - Hyeong-Ju Kang; Yongwoo Choi; Kimo Kim; In-Cheol Park; Jung-Wook Kim; Eul-Hwan Lee; Goo-Soo Gahang (Color Imaging: Processing, Hardcopy, and Applications, 2005)

SAT-based unbounded symbolic model checking. - Hyeong-Ju Kang; In-Cheol Park (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005)

Area-Efficient Prefilter Architecture for a CDMA Receiver. - Hyeong-Ju Kang; Seung Jae Lee 001; Byung-Do Yang (IEEE Trans. Circuits Syst. II Express Briefs, 2011)

A Low Power Content Addressable Memory Using Low Swing Search Lines. - Byung-Do Yang; Yong-Kyu Lee; Si-Woo Sung; Jae-Joong Min; Jae-Mun Oh; Hyeong-Ju Kang (IEEE Trans. Circuits Syst. I Regul. Pap., 2011)

Low-Power Time Deinterleaver for ISDB-T Receiver. - Hyeong-Ju Kang; Byung-Do Yang (IEEE Trans. Circuits Syst. II Express Briefs, 2012)

Area-efficient convolutional deinterleaver for mobile TV receiver. - Hyeong-Ju Kang; Hee Suk Seo; Jin Kwak (ACM Trans. Embed. Comput. Syst., 2013)

Real-Time Object Detection on 640x480 Image With VGG16+SSD. - Hyeong-Ju Kang (FPT, 2019)

Short floating-point representation for convolutional neural network inference. - Hyeong-Ju Kang (IEICE Electron. Express, 2019)

Area-Efficient Bidirectional Shift-Register Using Bidirectional Pulsed-Latches. - Ki-Chan Woo; Hyeong-Ju Kang; Byung-Do Yang (IEEE Trans. Circuits Syst. II Express Briefs, 2019)

Low-Area and Low-Power Latch-Based Thermometer-Code Shift-Register. - Ki-Chan Woo; Hyeong-Ju Kang; Byung-Do Yang (IEEE Trans. Circuits Syst. II Express Briefs, 2020)

Accelerator-Aware Pruning for Convolutional Neural Networks. - Hyeong-Ju Kang (IEEE Trans. Circuits Syst. Video Technol., 2020)

AoCStream: All-on-Chip CNN Accelerator With Stream-Based Line-Buffer Architecture. - Hyeong-Ju Kang (FPGA, 2023)

AoCStream: All-on-Chip CNN Accelerator with Stream-Based Line-Buffer Architecture and Accelerator-Aware Pruning. - Hyeong-Ju Kang; Byung-Do Yang (Sensors, 2023)