A 1.74mW/GHz 0.11-2.5GHz fast-locking, jitter-reducing, 180° phase-shift digital DLL with a window phase detector for LPDDR4 memory controllers. - Joo-Hyung Chae; Gi-Moon Hong; Jihwan Park; Mino Kim; Hyeongjun Ko; Woo-Yeol Shin; Hankyu Chi; Deog-Kyoon Jeong; Suhwan Kim 001 (A-SSCC, 2015)

A 4.35Gb/s/pin LPDDR4 I/O interface with multi-VOH level, equalization scheme, and duty-training circuit for mobile applications. - Hae-Kang Jung; Jaemo Yang; Jeonghun Lee; Hyeongjun Ko; Hyuk Lee; Taeksang Song; Jongjoo Shim; Sangkwon Lee; Keunsoo Song; Dongkyun Kim; Hyungsoo Kim; Yunsaing Kim (VLSIC, 2015)

An 8Gb/s adaptive DFE with level calibration using training data pattern for mobile DRAM interface. - Minchang Kim; Jihwan Park; Joo-Hyung Chae; Hyeongjun Ko; Mino Kim; Suhwan Kim 001 (ISOCC, 2017)

A 4266 Mb/s/pin LPDDR4 Interface With An Asynchronous Feedback CTLE and An Adaptive 3-Step Eye Detection Algorithm for Memory Controller. - Mino Kim; Joo-Hyung Chae; Sungphil Choi; Gi-Moon Hong; Hyeongjun Ko; Deog-Kyoon Jeong; Suhwan Kim 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2018)

A 20Gb/s Dual-Mode PAM4/NRZ Single-Ended Transmitter with RLM Compensation. - Changho Hyun; Hyeongjun Ko; Joo-Hyung Chae; Hyunkyu Park 002; Suhwan Kim 001 (ISCAS, 2019)

A 12.8-Gb/s Quarter-Rate Transmitter Using a 4: 1 Overlapped Multiplexing Driver Combined With an Adaptive Clock Phase Aligner. - Joo-Hyung Chae; Hyeongjun Ko; Jihwan Park; Suhwan Kim 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2019)

A Quadrature Clock Corrector for DRAM Interfaces, With a Duty-Cycle and Quadrature Phase Detector Based on a Relaxation Oscillator. - Joo-Hyung Chae; Hyeongjun Ko; Jihwan Park; Suhwan Kim 001 (IEEE Trans. Very Large Scale Integr. Syst., 2019)

A Controller PHY for Managed DRAM Solution With Damping-Resistor-Aided Pulse-Based Feed-Forward Equalizer. - Hyeongjun Ko; Mino Kim; Hyunkyu Park 002; Sangyoon Lee 006; Jaewook Kim; Suhwan Kim 001; Joo-Hyung Chae (IEEE J. Solid State Circuits, 2021)

13.1 A 35.4Gb/s/pin 16Gb GDDR7 with a Low-Power Clocking Architecture and PAM3 IO Circuitry. - Jaehyeok Yang; Hyeongjun Ko; Kyunghoon Kim; Hyunsu Park; Jihwan Park; Ji-Hyo Kang; Jin-Youp Cha; Seongjin Kim; Youngtaek Kim; Minsoo Park; Gangsik Lee; Keonho Lee; et al. (ISSCC, 2024)

A 28-Gb/s Single-Ended PAM-4 Receiver With T-Coil-Integrated Continuous-Time Linear Equalizer in 40-nm CMOS Technology. - Taeyang Sim; Sun-Ho Yeom; Hyunwoo Im; Youngmin Oh; Hyeongmin Seo; Hyeongjun Ko; Hankyu Chi; Hae-Kang Jung; Jaeduk Han (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

22.3 A 42Gb/s Single-Ended Hybrid-DFE PAM-3 Receiver for GDDR7 Memory Interfaces. - Boram Kim; Hankyu Chi; Hyeongjun Ko; Sang-Yeon Byeon; Sungkwon Lee; Changhyun Pyo; Seulgi Kim; Byungjun Kang; Eunji Song; Kwangjin Na; Jin-Youp Cha; Hyesoo Kim; et al. (ISSCC, 2025)