A 0.02mm2 100dB-DR Impedance Monitoring IC with PWM-Dual GRO Architecture. - Hyeonho Han; Woojun Choi; Youngcheol Chae (VLSI Circuits, 2019)

A Highly-Digital PWM-Based Impedance Monitoring IC with 143.2dB DR and 17.7fFrms Resolution. - Hyeonho Han; Woojun Choi; Jaehyun Kim; Jaesuk Sung; Heonjin Choi; Youngcheol Chae (VLSI Technology and Circuits, 2023)

A Highly Digital 143.2-dB DR Sub-1° Phase Error Impedance Monitoring IC With Pulsewidth Modulation Frontend. - Hyeonho Han; Byungchoul Park; Jaesuk Sung; Heonjin Choi; Youngcheol Chae (IEEE J. Solid State Circuits, 2024)

A 500-kS/s Continuous-Time Linear-Exponential Incremental ADC Achieving 90.1-dB DR and 103.1-dB SFDR. - Wonseon Lee; Hyeonho Han; Yigi Kwon; Seokho Yoon; Junghyun Yoon; Sanghoon Lee 009; Moon Hyung Jang; Youngcheol Chae (IEEE Trans. Circuits Syst. I Regul. Pap., 2025)