Wrong Path Events: Exploiting Unusual and Illegal Program Behavior for Early Misprediction Detection and Recovery. - David N. Armstrong; Hyesoon Kim; Onur Mutlu; Yale N. Patt (MICRO, 2004)

Cache Filtering Techniques to Reduce the Negative Impact of Useless Speculative Memory References on Processor Performance. - Onur Mutlu; Hyesoon Kim; David N. Armstrong; Yale N. Patt (SBAC-PAD, 2004)

Understanding the effects of wrong-path memory references on processor performance. - Onur Mutlu; Hyesoon Kim; David N. Armstrong; Yale N. Patt (WMPI, 2004)

Techniques for Efficient Processing in Runahead Execution Engines. - Onur Mutlu; Hyesoon Kim; Yale N. Patt (ISCA, 2005)

Wish Branches: Combining Conditional Branching and Predication for Adaptive Predicated Execution. - Hyesoon Kim; Onur Mutlu; Jared Stark; Yale N. Patt (MICRO, 2005)

Address-Value Delta (AVD) Prediction: Increasing the Effectiveness of Runahead Execution by Exploiting Regular Memory Allocation Patterns. - Onur Mutlu; Hyesoon Kim; Yale N. Patt (MICRO, 2005)

On Reusing the Results of Pre-Executed Instructions in a Runahead Execution Processor. - Onur Mutlu; Hyesoon Kim; Jared Stark; Yale N. Patt (IEEE Comput. Archit. Lett., 2005)

Using the First-Level Caches as Filters to Reduce the Pollution Caused by Speculative Memory References. - Onur Mutlu; Hyesoon Kim; David N. Armstrong; Yale N. Patt (Int. J. Parallel Program., 2005)

An Analysis of the Performance Impact of Wrong-Path Memory References on Out-of-Order and Runahead Execution Processors. - Onur Mutlu; Hyesoon Kim; David N. Armstrong; Yale N. Patt (IEEE Trans. Computers, 2005)

2D-Profiling: Detecting Input-Dependent Branches with a Single Input Data Set. - Hyesoon Kim; M. Aater Suleman; Onur Mutlu; Yale N. Patt (CGO, 2006)

Diverge-Merge Processor (DMP): Dynamic Predicated Execution of Complex Control-Flow Graphs Based on Frequently Executed Paths. - Hyesoon Kim; José A. Joao; Onur Mutlu; Yale N. Patt (MICRO, 2006)

Wish Branches: Enabling Adaptive and Aggressive Predicated Execution. - Hyesoon Kim; Onur Mutlu; Yale N. Patt; Jared Stark (IEEE Micro, 2006)

Efficient Runahead Execution: Power-Efficient Memory Latency Tolerance. - Onur Mutlu; Hyesoon Kim; Yale N. Patt (IEEE Micro, 2006)

Address-Value Delta (AVD) Prediction: A Hardware Technique for Efficiently Parallelizing Dependent Cache Misses. - Onur Mutlu; Hyesoon Kim; Yale N. Patt (IEEE Trans. Computers, 2006)

Profile-assisted Compiler Support for Dynamic Predication in Diverge-Merge Processors. - Hyesoon Kim; José A. Joao; Onur Mutlu; Yale N. Patt (CGO, 2007)

Feedback Directed Prefetching: Improving the Performance and Bandwidth-Efficiency of Hardware Prefetchers. - Santhosh Srinath; Onur Mutlu; Hyesoon Kim; Yale N. Patt (HPCA, 2007)

VPC prediction: reducing the cost of indirect branches via hardware-based dynamic devirtualization. - Hyesoon Kim; José A. Joao; Onur Mutlu; Chang Joo Lee; Yale N. Patt; Robert Cohn (ISCA, 2007)

Diverge-Merge Processor: Generalized and Energy-Efficient Dynamic Predication. - Hyesoon Kim; José A. Joao; Onur Mutlu; Yale N. Patt (IEEE Micro, 2007)

Improving the performance of object-oriented languages with dynamic predication of indirect jumps. - José A. Joao; Onur Mutlu; Hyesoon Kim; Rishi Agarwal; Yale N. Patt (ASPLOS, 2008)

Performance-aware speculation control using wrong path usefulness prediction. - Chang Joo Lee; Hyesoon Kim; Onur Mutlu; Yale N. Patt (HPCA, 2008)

Understanding performance, power and energy behavior in asymmetric multiprocessors. - Nagesh B. Lakshminarayana; Hyesoon Kim (ICCD, 2008)

Dynamic Predication of Indirect Jumps. - José A. Joao; Onur Mutlu; Hyesoon Kim; Yale N. Patt (IEEE Comput. Archit. Lett., 2008)

An analytical model for a GPU architecture with memory-level and thread-level parallelism awareness. - Sunpyo Hong; Hyesoon Kim (ISCA, 2009)

Qilin: exploiting parallelism on heterogeneous multiprocessors with adaptive mapping. - Chi-Keung Luk; Sunpyo Hong; Hyesoon Kim (MICRO, 2009)

Age based scheduling for asymmetric multiprocessors. - Nagesh B. Lakshminarayana; Jaekyu Lee; Hyesoon Kim (SC, 2009)

Virtual Program Counter (VPC) Prediction: Very Low Cost Indirect Branch Prediction Using Conditional Branch Prediction Hardware. - Hyesoon Kim; José A. Joao; Onur Mutlu; Chang Joo Lee; Yale N. Patt; Robert Cohn (IEEE Trans. Computers, 2009)

Design space exploration of the turbo decoding algorithm on GPUs. - Dongwon Lee 003; Marilyn Wolf; Hyesoon Kim (CASES, 2010)

An integrated GPU power and performance model. - Sunpyo Hong; Hyesoon Kim (ISCA, 2010)

SD3: A Scalable Approach to Dynamic Data-Dependence Profiling. - Minjang Kim; Hyesoon Kim; Chi-Keung Luk (MICRO, 2010)

Many-Thread Aware Prefetching Mechanisms for GPGPU Applications. - Jaekyu Lee; Nagesh B. Lakshminarayana; Hyesoon Kim; Richard W. Vuduc (MICRO, 2010)

TAP: A TLP-aware cache management policy for a CPU-GPU heterogeneous architecture. - Jaekyu Lee; Hyesoon Kim (HPCA, 2012)

Predicting Potential Speedup of Serial Code via Lightweight Profiling and Emulations with Memory Performance Model. - Minjang Kim; Pranith Kumar; Hyesoon Kim; Bevin Brett (IPDPS, 2012)

FLEXclusion: Balancing cache capacity and on-chip bandwidth via Flexible Exclusion. - Jaewoong Sim; Jaekyu Lee; Moinuddin K. Qureshi; Hyesoon Kim (ISCA, 2012)

A Mostly-Clean DRAM Cache for Effective Hit Speculation and Self-Balancing Dispatch. - Jaewoong Sim; Gabriel H. Loh; Hyesoon Kim; Mike O'Connor; Mithuna Thottethodi (MICRO, 2012)

Supporting virtual memory in GPGPU without supporting precise exceptions. - Hyesoon Kim (MSPC, 2012)

Design space exploration of memory model for heterogeneous computing. - Jieun Lim 001; Hyesoon Kim (MSPC, 2012)

A performance analysis framework for identifying potential benefits in GPGPU applications. - Jaewoong Sim; Aniruddha Dasgupta; Hyesoon Kim; Richard W. Vuduc (PPoPP, 2012)

DRAM Scheduling Policy for GPGPU Architectures Based on a Potential Function. - Nagesh B. Lakshminarayana; Jaekyu Lee; Hyesoon Kim; Jinwoo Shin (IEEE Comput. Archit. Lett., 2012)

When Prefetching Works, When It Doesn't, and Why. - Jaekyu Lee; Hyesoon Kim; Richard W. Vuduc (ACM Trans. Archit. Code Optim., 2012)

Performance Analysis and Tuning for General Purpose Graphics Processing Units (GPGPU) - Hyesoon Kim; Richard W. Vuduc; Sara S. Baghsorkhi; JeeWhan Choi; Wen-mei W. Hwu (Morgan & Claypool Publishers, 2012)

CHiP: A Profiler to Measure the Effect of Cache Contention on Scalability. - Bevin Brett; Pranith Kumar; Minjang Kim; Hyesoon Kim (IPDPS Workshops, 2013)

OpenCL Performance Evaluation on Modern Multi Core CPUs. - Joo Hwan Lee; Kaushik Patel; Nimit Nigania; Hyojong Kim; Hyesoon Kim (IPDPS Workshops, 2013)

SESH Framework: A Space Exploration Framework for GPU Application and Hardware Codesign. - Joo Hwan Lee; Jiayuan Meng; Hyesoon Kim (PMBS@SC, 2013)

Design space exploration of on-chip ring interconnection for a CPU-GPU heterogeneous architecture. - Jaekyu Lee; Si Li; Hyesoon Kim; Sudhakar Yalamanchili (J. Parallel Distributed Comput., 2013)

SD3: An Efficient Dynamic Data-Dependence Profiling Mechanism. - Minjang Kim; Nagesh B. Lakshminarayana; Hyesoon Kim; Chi-Keung Luk (IEEE Trans. Computers, 2013)

Adaptive virtual channel partitioning for network-on-chip in heterogeneous architectures. - Jaekyu Lee; Si Li; Hyesoon Kim; Sudhakar Yalamanchili (ACM Trans. Design Autom. Electr. Syst., 2013)

Harmonica: An FPGA-Based Data Parallel Soft Core. - Chad D. Kersey; Sudhakar Yalamanchili; Hyojong Kim; Nimit Nigania; Hyesoon Kim (FCCM, 2014)

Spare register aware prefetching for graph algorithms on GPUs. - Nagesh B. Lakshminarayana; Hyesoon Kim (HPCA, 2014)

TBPoint: Reducing Simulation Time for Large-Scale GPGPU Kernels. - Jen-Cheng Huang; Lifeng Nai; Hyesoon Kim; Hsien-Hsin S. Lee (IPDPS, 2014)

GPUMech: GPU Performance Modeling Technique Based on Interval Analysis. - Jen-Cheng Huang; Joo Hwan Lee; Hyesoon Kim; Hsien-Hsin S. Lee (MICRO, 2014)

Transparent Hardware Management of Stacked DRAM as Part of Memory. - Jaewoong Sim; Alaa R. Alameldeen; Zeshan Chishti; Chris Wilkerson; Hyesoon Kim (MICRO, 2014)

Power Modeling for GPU Architectures Using McPAT. - Jieun Lim 001; Nagesh B. Lakshminarayana; Hyesoon Kim; William J. Song; Sudhakar Yalamanchili; Wonyong Sung (ACM Trans. Design Autom. Electr. Syst., 2014)

BSSync: Processing Near Memory for Machine Learning Workloads with Bounded Staleness Consistency Models. - Joo Hwan Lee; Jaewoong Sim; Hyesoon Kim (PACT, 2015)

SIMT-based Logic Layers for Stacked DRAM Architectures: A Prototype. - Chad D. Kersey; Sudhakar Yalamanchili; Hyesoon Kim (MEMSYS, 2015)

Understanding Energy Aspects of Processing-near-Memory for HPC Workloads. - Hyojong Kim; Hyesoon Kim; Sudhakar Yalamanchili; Arun F. Rodrigues (MEMSYS, 2015)

Instruction Offloading with HMC 2.0 Standard: A Case Study for Graph Traversals. - Lifeng Nai; Hyesoon Kim (MEMSYS, 2015)

GraphBIG: understanding graph computing in the context of industrial solutions. - Lifeng Nai; Yinglong Xia; Ilie Gabriel Tanase; Hyesoon Kim; Ching-Yung Lin (SC, 2015)

Hardware Support for Safe Execution of Native Client Applications. - Dilan Manatunga; Joo Hwan Lee; Hyesoon Kim (IEEE Comput. Archit. Lett., 2015)

Accelerating Application Start-up with Nonvolatile Memory in Android Systems. - Hyojong Kim; Hong-Yeol Lim; Dilan Manatunga; Hyesoon Kim; Giho Park (IEEE Micro, 2015)

SP-CNN: A Scalable and Programmable CNN-Based Accelerator. - Dilan Manatunga; Hyesoon Kim; Saibal Mukhopadhyay (IEEE Micro, 2015)

OpenCL Performance Evaluation on Modern Multicore CPUs. - Joo Hwan Lee; Nimit Nigania; Hyesoon Kim; Kaushik Patel; Hyojong Kim (Sci. Program., 2015)

Block-Precise Processors: Low-Power Processors with Reduced Operand Store Accesses and Result Broadcasts. - Nagesh B. Lakshminarayana; Hyesoon Kim (IEEE Trans. Computers, 2015)

GREEN Cache: Exploiting the Disciplined Memory Model of OpenCL on GPUs. - Jaekyu Lee; Dong Hyuk Woo; Hyesoon Kim; Mani Azimi (IEEE Trans. Computers, 2015)

Analyzing Consistency Issues in HMC Atomics. - Pranith Kumar; Lifeng Nai; Hyesoon Kim (MEMSYS, 2016)

On the Internet of Things. - Vijay Janapa Reddi; Hyesoon Kim (IEEE Micro, 2016)

GraphPIM: Enabling Instruction-Level PIM Offloading in Graph Computing Frameworks. - Lifeng Nai; Ramyad Hadidi; Jaewoong Sim; Hyojong Kim; Pranith Kumar; Hyesoon Kim (HPCA, 2017)

Demystifying the characteristics of 3D-stacked memories: A case study for Hybrid Memory Cube. - Ramyad Hadidi; Bahar Asgari; Burhan Ahmad Mudassar; Saibal Mukhopadhyay; Sudhakar Yalamanchili; Hyesoon Kim (IISWC, 2017)

SimProf: A Sampling Framework for Data Analytic Workloads. - Jen-Cheng Huang; Lifeng Nai; Pranith Kumar; Hyojong Kim; Hyesoon Kim (IPDPS, 2017)

Lightweight SIMT core designs for intelligent 3D stacked DRAM. - Chad D. Kersey; Hyesoon Kim; Sudhakar Yalamanchili (MEMSYS, 2017)

Inferring Fine-grained Control Flow Inside SGX Enclaves with Branch Shadowing. - Sangho Lee 001; Ming-Wei Shih; Prasun Gera; Taesoo Kim; Hyesoon Kim; Marcus Peinado (USENIX Security Symposium, 2017)

CODA: Enabling Co-location of Computation and Data for Near-Data Processing. - Hyojong Kim; Ramyad Hadidi; Lifeng Nai; Hyesoon Kim; Nuwan Jayasena; Yasuko Eckert; Onur Kayiran; Gabriel H. Loh (CoRR, 2017)

Louvre: Light-weight Ordering Using Versioning for Release Consistency. - Pranith Kumar; Prasun Gera; Hyojong Kim; Hyesoon Kim (CoRR, 2017)

Exploring big graph computing - An empirical study from architectural perspective. - Lifeng Nai; Yinglong Xia; Ilie Gabriel Tanase; Hyesoon Kim (J. Parallel Distributed Comput., 2017)

CAIRO: A Compiler-Assisted Technique for Enabling Instruction-Level Offloading of Processing-In-Memory. - Ramyad Hadidi; Lifeng Nai; Hyojong Kim; Hyesoon Kim (ACM Trans. Archit. Code Optim., 2017)

Real-Time Image Recognition Using Collaborative IoT Devices. - Ramyad Hadidi; Jiashen Cao; Matthew Woodward; Michael S. Ryoo; Hyesoon Kim (ReQuEST@ASPLOS, 2018)

CoolPIM: Thermal-Aware Source Throttling for Efficient PIM Instruction Offloading. - Lifeng Nai; Ramyad Hadidi; He Xiao; Hyojong Kim; Jaewoong Sim; Hyesoon Kim (IPDPS, 2018)

Performance Characterisation and Simulation of Intel's Integrated GPU Architecture. - Prasun Gera; Hyojong Kim; Hyesoon Kim; Sunpyo Hong; Vinod George; Chi-Keung Luk (ISPASS, 2018)

Performance Implications of NoCs on 3D-Stacked Memories: Insights from the Hybrid Memory Cube. - Ramyad Hadidi; Bahar Asgari; Jeffrey S. Young 001; Burhan Ahmad Mudassar; Kartikay Garg; Tushar Krishna; Hyesoon Kim (ISPASS, 2018)

Musical Chair: Efficient Real-Time Recognition Using Collaborative IoT Devices. - Ramyad Hadidi; Jiashen Cao; Matthew Woodward; Michael S. Ryoo; Hyesoon Kim (CoRR, 2018)

Distributed Perception by Collaborative Robots. - Ramyad Hadidi; Jiashen Cao; Matthew Woodward; Michael S. Ryoo; Hyesoon Kim (IEEE Robotics Autom. Lett., 2018)

CODA: Enabling Co-location of Computation and Data for Multiple GPU Systems. - Hyojong Kim; Ramyad Hadidi; Lifeng Nai; Hyesoon Kim; Nuwan Jayasena; Yasuko Eckert; Onur Kayiran; Gabriel H. Loh (ACM Trans. Archit. Code Optim., 2018)

StaleLearn: Learning Acceleration with Asynchronous Synchronization Between Model Replicas on PIM. - Joo Hwan Lee; Hyesoon Kim (IEEE Trans. Computers, 2018)

POSTER: Tango: An Optimizing Compiler for Just-In-Time RTL Simulation. - Blaise-Pascal Tine; Sudhakar Yalamanchili; Hyesoon Kim; Jeffrey S. Vetter (PACT, 2019)

Translating CUDA to OpenCL for Hardware Generation using Neural Machine Translation. - Yonghae Kim; Hyesoon Kim (CGO, 2019)

Video analytics from edge to server: work-in-progress. - Jiashen Cao; Ramyad Hadidi; Joy Arulraj; Hyesoon Kim (CODES+ISSS, 2019)

LODESTAR: Creating Locally-Dense CNNs for Efficient Inference on Systolic Arrays. - Bahar Asgari; Ramyad Hadidi; Hyesoon Kim; Sudhakar Yalamanchili (DAC, 2019)

Robustly Executing DNNs in IoT Systems Using Coded Distributed Computing. - Ramyad Hadidi; Jiashen Cao; Michael S. Ryoo; Hyesoon Kim (DAC, 2019)

FlashGPU: Placing New Flash Next to GPU Cores. - Jie Zhang 048; Miryeong Kwon; Hyojong Kim; Hyesoon Kim; Myoungsoo Jung (DAC, 2019)

Capella: Customizing Perception for Edge Devices by Efficiently Allocating FPGAs to DNNs. - Younmin Bae; Ramyad Hadidi; Bahar Asgari; Jiashen Cao; Hyesoon Kim (FPL, 2019)

Characterizing the Deployment of Deep Neural Networks on Commercial Edge Devices. - Ramyad Hadidi; Jiashen Cao; Yilun Xie; Bahar Asgari; Tushar Krishna; Hyesoon Kim (IISWC, 2019)

Empirical Investigation of Stale Value Tolerance on Parallel RNN Training. - Joo Hwan Lee; Hyesoon Kim (ISPASS, 2019)

Characterizing the Execution of Deep Neural Networks on Collaborative Robots and Edge Devices. - Matthew L. Merck; Bingyao Wang; Lixing Liu; Chunjun Jia; Arthur Siqueira; Qiusen Huang; Abhijeet Saraha; Dongsuk Lim; Jiashen Cao; Ramyad Hadidi; Hyesoon Kim (PEARC, 2019)

Collaborative Execution of Deep Neural Networks on Internet of Things Devices. - Ramyad Hadidi; Jiashen Cao; Michael S. Ryoo; Hyesoon Kim (CoRR, 2019)

A Case Study: Exploiting Neural Machine Translation to Translate CUDA to OpenCL. - Yonghae Kim; Hyesoon Kim (CoRR, 2019)

Thermal-aware processing-in-memory instruction offloading. - Lifeng Nai; Ramyad Hadidi; He Xiao; Hyojong Kim; Jaewoong Sim; Hyesoon Kim (J. Parallel Distributed Comput., 2019)

ERIDANUS: Efficiently Running Inference of DNNs Using Systolic Arrays. - Bahar Asgari; Ramyad Hadidi; Hyesoon Kim; Sudhakar Yalamanchili (IEEE Micro, 2019)

Batch-Aware Unified Memory Management in GPUs for Irregular Workloads. - Hyojong Kim; Jaewoong Sim; Prasun Gera; Ramyad Hadidi; Hyesoon Kim (ASPLOS, 2020)

PISCES: Power-Aware Implementation of SLAM by Customizing Efficient Sparse Algebra. - Bahar Asgari; Ramyad Hadidi; Nima Shoghi Ghaleshahi; Hyesoon Kim (DAC, 2020)

ASCELLA: Accelerating Sparse Computation by Enabling Stream Accesses to Memory. - Bahar Asgari; Ramyad Hadidi; Hyesoon Kim (DATE, 2020)

Tango: An Optimizing Compiler for Just-In-Time RTL Simulation. - Blaise-Pascal Tine; Sudhakar Yalamanchili; Hyesoon Kim (DATE, 2020)

Proposing a Fast and Scalable Systolic Array for Matrix Multiplication. - Bahar Asgari; Ramyad Hadidi; Hyesoon Kim (FCCM, 2020)

Cash: A Single-Source Hardware-Software Codesign Framework for Rapid Prototyping. - Blaise Tine; Fares Elsabbagh; Seyong Lee; Jeffrey S. Vetter; Hyesoon Kim (FPGA, 2020)

Productive Hardware Designs using Hybrid HLS-RTL Development. - Blaise Tine; Seyong Lee; Jeffrey S. Vetter; Hyesoon Kim (FPGA, 2020)

RISC-V FPGA Platform Toward ROS-Based Robotics Application. - Jaewon Lee; Hanning Chen; Jeffrey S. Young 001; Hyesoon Kim (FPL, 2020)

ALRESCHA: A Lightweight Reconfigurable Sparse-Computation Accelerator. - Bahar Asgari; Ramyad Hadidi; Tushar Krishna; Hyesoon Kim; Sudhakar Yalamanchili (HPCA, 2020)

MEISSA: Multiplying Matrices Efficiently in a Scalable Systolic Architecture. - Bahar Asgari; Ramyad Hadidi; Hyesoon Kim (ICCD, 2020)

Understanding the Software and Hardware Stacks of a General-Purpose Cognitive Drone. - Sam Jijina; Adriana Amyette; Nima Shoghi Ghaleshahi; Ramyad Hadidi; Hyesoon Kim (ISPASS, 2020)

Neural Network Weight Compression with NNW-BDI. - Andrei Bersatti; Nima Shoghi; Hyesoon Kim (MEMSYS, 2020)

Things to Consider to Enable Dynamic Graphs in Processing-in-Memory. - Euna Kim; Hyesoon Kim (MEMSYS, 2020)

Parallel Hash Table Design for NDP Systems. - Pranith Kumar; Hyesoon Kim (MEMSYS, 2020)

Hardware-based Always-On Heap Memory Safety. - Yonghae Kim; Jaekyu Lee; Hyesoon Kim (MICRO, 2020)

Vortex: OpenCL Compatible RISC-V GPGPU. - Fares Elsabbagh; Blaise Tine; Priyadarshini Roshan; Ethan Lyons; Euna Kim; Da Eun Shim; Lingjun Zhu; Sung Kyu Lim; Hyesoon Kim (CoRR, 2020)

Edge-Tailored Perception: Fast Inferencing in-the-Edge with Efficient Model Distribution. - Ramyad Hadidi; Bahar Asgari; Jiashen Cao; Younmin Bae; Hyojong Kim; Michael S. Ryoo; Hyesoon Kim (CoRR, 2020)

Reducing Inference Latency with Concurrent Architectures for Image Recognition. - Ramyad Hadidi; Jiashen Cao; Michael S. Ryoo; Hyesoon Kim (CoRR, 2020)

Secure Location-Aware Authentication and Communication for Intelligent Transportation Systems. - Nima Shoghi Ghaleshahi; Ramyad Hadidi; Jaewon Lee; Jun Chen; Arthur Siqueira; Rahul Rajan; Shaan Dhawan; Pooya Shoghi Ghalehshahi; Hyesoon Kim (CoRR, 2020)

Copernicus: Characterizing the Performance Implications of Compression Formats Used in Sparse Workloads. - Bahar Asgari; Ramyad Hadidi; Joshua Dierberger; Charlotte Steinichen; Hyesoon Kim (CoRR, 2020)

Toward Collaborative Inferencing of Deep Neural Networks on Internet-of-Things Devices. - Ramyad Hadidi; Jiashen Cao; Michael S. Ryoo; Hyesoon Kim (IEEE Internet Things J., 2020)

The 2019 Top Picks in Computer Architecture. - Hyesoon Kim (IEEE Micro, 2020)

Traversing Large Graphs on GPUs with Unified Memory. - Prasun Gera; Hyojong Kim; Piyush Sao; Hyesoon Kim; David A. Bader (Proc. VLDB Endow., 2020)

Quantifying the design-space tradeoffs in autonomous drones. - Ramyad Hadidi; Bahar Asgari; Sam Jijina; Adriana Amyette; Nima Shoghi; Hyesoon Kim (ASPLOS, 2021)

RASA: Efficient Register-Aware Systolic Array Matrix Engine for CPU. - Geonhwa Jeong; Eric Qin 001; Ananda Samajdar; Christopher J. Hughes; Sreenivas Subramoney; Hyesoon Kim; Tushar Krishna (DAC, 2021)

FAFNIR: Accelerating Sparse Gathering by Using Efficient Near-Memory Intelligent Reduction. - Bahar Asgari; Ramyad Hadidi; Jiashen Cao; Da Eun Shim; Sung Kyu Lim; Hyesoon Kim (HPCA, 2021)

Copernicus: Characterizing the Performance Implications of Compression Formats Used in Sparse Workloads. - Bahar Asgari; Ramyad Hadidi; Joshua Dierberger; Charlotte Steinichen; Amaan Marfatia; Hyesoon Kim (IISWC, 2021)

Vortex: Extending the RISC-V ISA for GPGPU and 3D-Graphics. - Blaise Tine; Krishna Praveen Yalamarthy; Fares Elsabbagh; Hyesoon Kim (MICRO, 2021)

SmaQ: Smart Quantization for DNN Training by Exploiting Value Clustering. - Nima Shoghi; Andrei Bersatti; Moinuddin K. Qureshi; Hyesoon Kim (IEEE Comput. Archit. Lett., 2021)

THIA: Accelerating Video Analytics using Early Inference and Fine-Grained Query Planning. - Jiashen Cao; Ramyad Hadidi; Joy Arulraj; Hyesoon Kim (CoRR, 2021)

Creating Robust Deep Neural Networks With Coded Distributed Computing for IoT Systems. - Ramyad Hadidi; Jiashen Cao; Hyesoon Kim (CoRR, 2021)

Supporting CUDA for an extended RISC-V GPU architecture. - Ruobing Han; Blaise Tine; Jaewon Lee; Jaewoong Sim; Hyesoon Kim (CoRR, 2021)

Vortex: Extending the RISC-V ISA for GPGPU and 3D-GraphicsResearch. - Blaise Tine; Fares Elsabbagh; Krishna Praveen Yalamarthy; Hyesoon Kim (CoRR, 2021)

COX: CUDA on X86 by Exposing Warp-Level Functions to CPUs. - Ruobing Han; Jaewon Lee; Jaewoong Sim; Hyesoon Kim (CoRR, 2021)

Efficiently Solving Partial Differential Equations in a Partially Reconfigurable Specialized Hardware. - Bahar Asgari; Ramyad Hadidi; Tushar Krishna; Hyesoon Kim; Sudhakar Yalamanchili (IEEE Trans. Computers, 2021)

Maia: Matrix Inversion Acceleration Near Memory. - Bahar Asgari; Dheeraj Ramchandani; Amaan Marfatia; Hyesoon Kim (FPL, 2022)

Accelerating Graphic Rendering on Programmable RISC-V GPUs. - Blaise Tine; Varun Saxena; Santosh Srivatsan; Joshua R. Simpson; Fadi Alzammar; Liam Paul Cooper; Sam Jijina; Swetha Rajagoplan; Tejaswini Anand Kumar; Jeffrey Young 001; Hyesoon Kim (HCS, 2022)

Securing GPU via region-based bounds checking. - Jaewon Lee; Yonghae Kim; Jiashen Cao; Euna Kim; Jaekyu Lee; Hyesoon Kim (ISCA, 2022)

FiGO: Fine-Grained Query Optimization in Video Analytics. - Jiashen Cao; Karan Sarkar; Ramyad Hadidi; Joy Arulraj; Hyesoon Kim (SIGMOD Conference, 2022)

CuPBoP: CUDA for Parallelized and Broad-range Processors. - Ruobing Han; Jun Chen; Bhanu Garg; Jeffrey Young 001; Jaewoong Sim; Hyesoon Kim (CoRR, 2022)

COX : Exposing CUDA Warp-level Functions to CPUs. - Ruobing Han; Jaewon Lee; Jaewoong Sim; Hyesoon Kim (ACM Trans. Archit. Code Optim., 2022)

Skybox: Open-Source Graphic Rendering on Programmable RISC-V GPUs. - Blaise Tine; Varun Saxena; Santosh Srivatsan; Joshua R. Simpson; Fadi Alzammar; Liam Cooper; Hyesoon Kim (ASPLOS (3), 2023)

Creating Robust Deep Neural Networks with Coded Distributed Computing for IoT. - Ramyad Hadidi; Jiashen Cao; Bahar Asgari; Hyesoon Kim (EDGE, 2023)

Reducing Inference Latency with Concurrent Architectures for Image Recognition at Edge. - Ramyad Hadidi; Jiashen Cao; Michael S. Ryoo; Hyesoon Kim (EDGE, 2023)

Context-Aware Task Handling in Resource-Constrained Robots with Virtualization. - Ramyad Hadidi; Nima Shoghi Ghaleshahi; Bahar Asgari; Hyesoon Kim (EDGE, 2023)

Spica: Exploring FPGA Optimizations to Enable an Efficient SpMV Implementation for Computations at Edge. - Dheeraj Ramchandani; Bahar Asgari; Hyesoon Kim (EDGE, 2023)

VEGETA: Vertically-Integrated Extensions for Sparse/Dense GEMM Tile Acceleration on CPUs. - Geonhwa Jeong; Sana Damani; Abhimanyu Rajeshkumar Bambhaniya; Eric Qin 001; Christopher J. Hughes; Sreenivas Subramoney; Hyesoon Kim; Tushar Krishna (HPCA, 2023)

Traversing Large Compressed Graphs on GPUs. - Prasun Gera; Hyesoon Kim (IPDPS, 2023)

EHT-SR: An Entropy-Based Hybrid Approach for Faster Super-Resolution. - Abhilash Dharmavarapu; Stefano Petrangeli; Jiashen Cao; Hyesoon Kim (ISM, 2023)

Extending the Life of Old Systems with More Memory. - Euna Kim; Andrei Bersatti; Hyesoon Kim (MEMSYS, 2023)

CuPBoP: A Framework to Make CUDA Portable. - Ruobing Han; Jun Chen; Bhanu Garg; Jeffrey Young 001; Jaewoong Sim; Hyesoon Kim (PPoPP, 2023)

CuPBoP-AMD: Extending CUDA to AMD Platforms. - Jun Chen; Xule Zhou; Hyesoon Kim (SC Workshops, 2023)

Unified Co-Simulation Framework for Autonomous UAVs. - Sri Ranganathan Palaniappan; Varun Pateel; Sam Jijina; Jeffrey Young 001; Hyesoon Kim (PEARC, 2023)

Mitigating Timing-Based NoC Side-Channel Attacks With LLC Remapping. - Anurag Kar; Xueyang Liu; Yonghae Kim; Gururaj Saileshwar; Hyesoon Kim; Tushar Krishna (IEEE Comput. Archit. Lett., 2023)

Hardware-Assisted Code-Pointer Tagging for Forward-Edge Control-Flow Integrity. - Yonghae Kim; Anurag Kar; Jaewon Lee; Jaekyu Lee; Hyesoon Kim (IEEE Comput. Archit. Lett., 2023)

Revisiting Query Performance in GPU Database Systems. - Jiashen Cao; Rathijit Sen; Matteo Interlandi; Joy Arulraj; Hyesoon Kim (CoRR, 2023)

RV-CURE: A RISC-V Capability Architecture for Full Memory Safety. - Yonghae Kim; Anurag Kar; Jaewon Lee; Jaekyu Lee; Hyesoon Kim (CoRR, 2023)

GPU Database Systems Characterization and Optimization. - Jiashen Cao; Rathijit Sen; Matteo Interlandi; Joy Arulraj; Hyesoon Kim (Proc. VLDB Endow., 2023)

Exponentially Expanding the Phase-Ordering Search Space via Dormant Information. - Ruobing Han; Hyesoon Kim (CC, 2024)

Enabling Fine-Grained Incremental Builds by Making Compiler Stateful. - Ruobing Han; Jisheng Zhao; Hyesoon Kim (CGO, 2024)

Towards "True" GPU Performance Scaling for OpenGPU. - Blaise Tine; Hyesoon Kim (HCS, 2024)

Understanding Performance Implications of LLM Inference on CPUs. - Seonjin Na; Geonhwa Jeong; Byung Hoon Ahn; Jeffrey Young 001; Tushar Krishna; Hyesoon Kim (IISWC, 2024)

Comparative Analysis of Executing GPU Applications on FPGA: HLS vs. Soft GPU Approaches. - Chihyo Ahn; Shinnung Jeong; Liam Paul Cooper; Nicholas Parnenzini; Hyesoon Kim (IPDPS (Workshops), 2024)

Barre Chord: Efficient Virtual Memory Translation for Multi-Chip-Module GPUs. - Yuan Feng; Seonjin Na; Hyesoon Kim; Hyeran Jeon (ISCA, 2024)

Unleashing CPU Potential for Executing GPU Programs Through Compiler/Runtime Optimizations. - Ruobing Han; Jisheng Zhao; Hyesoon Kim (MICRO, 2024)

Hydro: Adaptive Query Processing of ML Queries. - Gaurav Tarlok Kakkar; Jiashen Cao; Aubhro Sengupta; Joy Arulraj; Hyesoon Kim (CoRR, 2024)

Towards Performance-Aware Allocation for Accelerated Machine Learning on GPU-SSD Systems. - Ayush Gundawar; Euijun Chung; Hyesoon Kim (CoRR, 2024)

Quantifying CO2 Emission Reduction Through Spatial Partitioning in Deep Learning Recommendation System Workloads. - Andrei Bersatti; Euna Kim; Hyesoon Kim (IEEE Micro, 2024)

CuPBoP: Making CUDA a Portable Language. - Ruobing Han; Jun Chen; Bhanu Garg; Xule Zhou; John Lu; Jeffrey Young 001; Jaewoong Sim; Hyesoon Kim (ACM Trans. Design Autom. Electr. Syst., 2024)

Buffer Management for Out-of-GPU LLM Execution. - Jiashen Cao; Joy Arulraj; Hyesoon Kim (DEEM@SIGMOD, 2025)

SoftCUDA: Running CUDA on Softcore GPU. - Chihyo Ahn; Ruobing Han; Udit Subramanya; Jisheng Zhao; Blaise Tine; Hyesoon Kim (FCCM, 2025)

SparseWeaver: Converting Sparse Operations as Dense Operations on GPUs for Graph Workloads. - Shinnung Jeong; Liam Paul Coopert; Ju Min Lee; Heelim Choi; Nicholas Parnenzini; Chihyo Ahn; Yongwoo Lee 001; Hanjun Kim 001; Hyesoon Kim (HPCA, 2025)

Let-Me-In: (Still) Employing In-pointer Bounds Metadata for Fine-grained GPU Memory Safety. - Jaewon Lee; Euijun Chung; Saurabh Singh; Seonjin Na; Yonghae Kim; Jaekyu Lee; Hyesoon Kim (HPCA, 2025)

Analysis of the RISC-V Vector Extension for Vulkan Graphics Kernels. - Martin Troiber; Martin Schulz 001; Blaise Tine; Hyesoon Kim (ISPASS, 2025)

Contention-Aware GPU Thread Block Scheduler for Efficient GPU-SSD. - Xueyang Liu; Seonjin Na; Euijun Chung; Jiashen Cao; Jing Yang; Hyesoon Kim (IEEE Comput. Archit. Lett., 2025)

Hardware vs. Software Implementation of Warp-Level Features in Vortex RISC-V GPU. - Huanzhi Pu; Rishabh Ravi; Shinnung Jeong; Udit Subramanya; Euijun Chung; Jisheng Zhao; Chihyo Ahn; Hyesoon Kim (CoRR, 2025)

Aero: Adaptive Query Processing of ML Queries. - Gaurav Tarlok Kakkar; Jiashen Cao; Aubhro Sengupta; Joy Arulraj; Hyesoon Kim (Proc. ACM Manag. Data, 2025)