A technique to reduce flicker noise up-conversion in CMOS LC voltage-controlled oscillators. - Hyman Shanan; Michael Peter Kennedy (ESSCIRC, 2004)

A highly integrated low-power 2.4GHz transceiver using a direct-conversion diversity receiver in 0.18µm CMOS for IEEE802.15.4 WPAN. - Guido Retz; Hyman Shanan; Kenneth Mulvaney; Kenneth O'Mahony; Miguel Chanca; Pat Crowley; Charley Billon; Muhammad Kalimuddin Khan; Philip Quinlan (ISSCC, 2009)

A 2.4GHz 2Mb/s versatile PLL-based transmitter using digital pre-emphasis and auto calibration in 0.18µm CMOS for WPAN. - Hyman Shanan; Guido Retz; Kenneth Mulvaney; Philip Quinlan (ISSCC, 2009)

Radio transceivers for wireless personal area networks using IEEE802.15.4. - Guido Retz; Hyman Shanan; Kenneth Mulvaney; Shane O'Mahony; Miguel Chanca; Pat Crowley; Charley Billon; Muhammad Kalimuddin Khan; Jesus Javier Lopez Orive; Philip Quinlan (IEEE Commun. Mag., 2009)

High speed, high accuracy fractional-N frequency synthesizer using nested mixed-radix digital Δ-Σ modulators. - Michael Peter Kennedy; Brian Fitzgibbon; Austin Harney; Hyman Shanan; Mike Keaveney (ESSCIRC, 2013)

0.3-4.3 GHz Frequency-Accurate Fractional-N Frequency Synthesizer With Integrated VCO and Nested Mixed-Radix Digital Δ-Σ Modulator-Based Divider Controller. - Michael Peter Kennedy; Hongjia Mo; Brian Fitzgibbon; Austin Harney; Hyman Shanan; Mike Keaveney (IEEE J. Solid State Circuits, 2014)

An Eight-Phase 40GHz RTWO in 28nm CMOS with Phase Noise Reduction Via Head and Tail Filtering. - Salvatore Galeone; Michael Peter Kennedy; Karim Ahmed; Hyman Shanan; Mike Keaveney (ICECS, 2019)

A 9-to-12GHz Coupled-RTWO FMCW ADPLL with 97fs RMS Jitter, -120dBc/Hz PN at 1MHz Offset, and With Retrace Time of 12.5ns and 2μs Chirp Settling Time. - Hyman Shanan; Declan Dalton; Vamshi Chillara; Pablo Dato (ISSCC, 2022)