A 64 Channel Programmable Closed-Loop Neurostimulator With 8 Channel Neural Amplifier and Logarithmic ADC. - Jongwoo Lee; Hyo-Gyuem Rhew; Daryl R. Kipke; Michael P. Flynn (IEEE J. Solid State Circuits, 2010)

A 22Gb/s, 10mm on-chip serial link over lossy transmission line with resistive termination. - Hyo-Gyuem Rhew; Michael P. Flynn; JunYoung Park (ESSCIRC, 2012)

A wirelessly powered log-based closed-loop deep brain stimulation SoC with two-way wireless telemetry for treatment of neurological disorders. - Hyo-Gyuem Rhew; Jaehun Jeong; Jeffrey A. Fredenburg; Sunjay Dodani; Parag G. Patil; Michael P. Flynn (VLSIC, 2012)

A Fully Self-Contained Logarithmic Closed-Loop Deep Brain Stimulation SoC With Wireless Telemetry and Wireless Power Management. - Hyo-Gyuem Rhew; Jaehun Jeong; Jeffrey A. Fredenburg; Sunjay Dodani; Parag G. Patil; Michael P. Flynn (IEEE J. Solid State Circuits, 2014)

3.2 A 320mW 32Gb/s 8b ADC-based PAM-4 analog front-end with programmable gain control and analog peaking in 28nm CMOS. - Delong Cui; Heng Zhang; Nick Huang; Ali Nazemi; Burak Çatli; Hyo-Gyuem Rhew; Bo Zhang 029; Afshin Momtaz; Jun Cao 001 (ISSCC, 2016)

A 72GS/s, 8-bit DAC-based Wireline Transmitter in 4nm FinFET CMOS for 200+Gb/s Serial Links. - Timothy O. Dickson; Zeynep Toprak Deniz; Martin Cochet; Marcel A. Kossel; Thomas Morf; Young-Ho Choi; Pier Andrea Francese; Matthias Brändli; Troy J. Beukema; Christian W. Baks; Jonathan E. Proesel; John F. Bulzacchelli; et al. (VLSI Technology and Circuits, 2022)

An 8-bit 56GS/s 64x Time-Interleaved ADC with Bootstrapped Sampler and Class-AB Buffer in 4nm CMOS. - Serdar S. Yonar; Pier Andrea Francese; Matthias Brändli; Marcel A. Kossel; Thomas Morf; Jonathan E. Proesel; Sergey V. Rylov; Herschel A. Ainspan; Martin Cochet; Zeynep Toprak Deniz; Timothy O. Dickson; Troy J. Beukema; et al. (VLSI Technology and Circuits, 2022)

A 4nm 1.15TB/s HBM3 Interface with Resistor-Tuned Offset-Calibration and In-Situ Margin-Detection. - Kwanyeob Chae; Jiyeon Park; Jaegeun Song; Billy Koo; Jihun Oh; Shinyoung Yi 002; Won Lee; Dongha Kim; Taekyung Yeo; Kyeongkeun Kang; Sangsoo Park; Eunsu Kim; et al. (ISSCC, 2023)

A 4nm 32Gb/s 8Tb/s/mm Die-to-Die Chiplet Using NRZ Single-Ended Transceiver With Equalization Schemes And Training Techniques. - Kihwan Seong; Donguk Park; Gyeom-Je Bae; Hyunwoo Lee; Youngseob Suh; Wooseuk Oh; Hyemun Lee; Juyoung Kim; Takgun Lee; Geonhoo Mo; Sukhyun Jung; Dongcheol Choi; et al. (ISSCC, 2023)

A 72-GS/s, 8-Bit DAC-Based Wireline Transmitter in 4-nm FinFET CMOS for 200+ Gb/s Serial Links. - Timothy O. Dickson; Zeynep Toprak Deniz; Martin Cochet; Troy J. Beukema; Marcel A. Kossel; Thomas Morf; Young-Ho Choi; Pier Andrea Francese; Matthias Brändli; Christian W. Baks; Jonathan E. Proesel; John F. Bulzacchelli; et al. (IEEE J. Solid State Circuits, 2023)

18.1 A 600Gb/s DP-QAM64 Coherent Optical Transceiver Frontend with 4x105GS/s 8b ADC/DAC in 16nm CMOS. - Guansheng Li; Adesh Garg; Tim He; Ullas Singh; Jiawen Zhang; Lakshmi P. Rao; Chang Liu; Meisam Honarvar Nazari; Yang Liu; Yong Liu; Heng Zhang; Tamer A. Ali 001; et al. (ISSCC, 2024)

16.8 A 60Mb/s TRNG with PVT-Variation-Tolerant Design Based on STR in 4nm. - Jieun Park; Yong Ki Lee; Bohdan Karpinskyy; Yunhyeok Choi; Jonghoon Shin; Hyo-Gyuem Rhew; Jongshin Shin (ISSCC, 2024)

13.10 A 4nm 48Gb/s/wire Single-Ended NRZ Parallel Transceiver with Offset-Calibration and Equalization Schemes for Next-Generation Memory Interfaces and Chiplets. - Kihwan Seong; Wooseuk Oh; Hyunwoo Lee; Gyeom-Je Bae; Youngseob Suh; Hyemun Lee; Juyoung Kim; Eunsu Kim; Yeongeon Kang; Gunhu Mo; Youjin Lee; Mingyeong Kim; et al. (ISSCC, 2024)

A 4-nm 1.15 TB/s HBM3 Interface With Resistor-Tuned Offset Calibration and In Situ Margin Detection. - Kwanyeob Chae; Jaegeun Song; Yoonjae Choi; Jiyeon Park; Billy Koo; Jihun Oh; Shinyoung Yi 002; Won Lee; Dongha Kim; Kyeongkeun Kang; Eunsu Kim; Juyoung Kim; et al. (IEEE J. Solid State Circuits, 2024)

An 800GbE PAM-4 PHY Transceiver that Supports 42dB Copper and Direct-Drive Optical Applications in 7nm. - Chang Liu; Burak Çatli; Yong Liu; Anand Vasani; Guansheng Li; Kun Chua; Lakshmi P. Rao; Yang Liu; Xin Meng; Jiawen Zhang; Tim He; Batu Dayanik; et al. (CICC, 2025)

An Efficient Vth-Tilting PUF Design in 3nm GAA and 8nm FinFET Technologies. - Bohdan Karpinskyy; Yong Ki Lee; Sumin Noh; Yunhyeok Choi; Jieun Park; Jisu Kang; Taewook Park; Eunhye Oh; Gapkyung Kim; Sungha Lee; Hyunwoo Ko; Jonghoon Shin; et al. (ISSCC, 2025)