A 1.2V 30nm 1.6Gb/s/pin 4Gb LPDDR3 SDRAM with input skew calibration and enhanced control scheme. - Yong-Cheol Bae; Joon-Young Park; Sang Jae Rhee; Seung-Bum Ko; Yonggwon Jeong; Kwang-Sook Noh; Young Hoon Son; Jaeyoun Youn; Yonggyu Chu; Hyunyoon Cho; Mijo Kim; Daesik Yim; et al. (ISSCC, 2012)

A HDMI-to-MHL video format conversion system-on-chip (SoC) for mobile handset in a 130-nm CMOS technology. - Hyochang Kim 002; Jaewoo Park; Woosang Han; Kyuhwan Oh; Taekjun Ahn; Jun-Gi Jo; Ook Kim; Changsik Yoo (ICCE, 2016)

Duty-cycle and phase spacing error correction circuit for high-speed serial link. - Hyochang Kim 002; Ook Kim; Changsik Yoo (IEICE Electron. Express, 2017)

A 6-Gb/s Wireline Receiver With Intrapair Skew Compensation and Three-Tap Decision-Feedback Equalizer in 28-nm CMOS. - Hyochang Kim 002; Changsik Yoo (IEEE Trans. Very Large Scale Integr. Syst., 2020)

A 16 GB 1024 GB/s HBM3 DRAM With Source-Synchronized Bus Design and On-Die Error Control Scheme for Enhanced RAS Features. - Yesin Ryu; Sung-Gi Ahn; Jaehoon Lee 005; Jaewon Park; Yong-Ki Kim; Hyochang Kim 002; Yeong Geol Song; Han-Won Cho; Sunghye Cho; Seung Ho Song; Haesuk Lee; Useung Shin; et al. (IEEE J. Solid State Circuits, 2023)

A 16-Gb/s/Wire 4-Wire Short-Haul Transceiver With Balanced Single-Ended Signaling (BASES) in 28-nm CMOS. - Hyochang Kim 002; Hyeongmin Seo; Hyuntae Kim; Changsik Yoo; Jaeduk Han (IEEE Trans. Circuits Syst. II Express Briefs, 2023)