A 16Gb 27Gb/s/pin T-coil based GDDR6 DRAM with Merged-MUX TX, Optimized WCK Operation, and Alternative-Data-Bus. - Daewoong Lee; Hye-Jung Kwon; Daehyun Kwon; Jaehyeok Baek; Chulhee Cho; Sanghoon Kim; Donggun An; Chulsoon Chang; Unhak Lim; Jiyeon Im; Wonju Sung; Hye-Ran Kim; et al. (ISSCC, 2022)

Enhanced DRAM Single Bit Characteristics from Process Control of Chlorine. - Taiuk Rim; Kyosuk Che; Sehyun Kwon; Jin-Seong Lee; Jeonghoon Oh; Hyodong Ban; Jooyoung Lee (IRPS, 2023)

Analysis of Intermittent Single-bit Failure on 10-nm node generation DRAM Devices. - Hyewon Seo; Taiuk Rim; Eunsun Lee; Sekyoung Jang; Kyosuk Chae; Jeonghoon Oh; Hyodong Ban; Jooyoung Lee (IRPS, 2023)

Investigation on NBTI Control Techniques of HKMG Transistors for Low-power DRAM applications. - Wonju Sung; Hyun Seung Kim; Jung Hoon Han; Seguen Park; Jeonghoon Oh; Hyodong Ban; Jooyoung Lee (IRPS, 2023)

14nm DRAM Development and Manufacturing. - Kanguk Kim; Youngwoo Son; Hoin Ryu; Byunghyun Lee; Jooncheol Kim; Hyunsu Shin; Joonyoung Kang; Jihun Kim; Shinwoo Jeong; Kyosuk Chae; Dongkak Lee; Ilwoo Jung; et al. (VLSI Technology and Circuits, 2023)

A 16-Gb T-Coil-Based GDDR6 DRAM With Merged-MUX TX, Optimized WCK Operation, and Alternative-Data-Bus Achieving 27-Gb/s/Pin in NRZ. - Daewoong Lee; Jaehyeok Baek; Hye-Jung Kwon; Daehyun Kwon; Chulhee Cho; Sang-Hoon Kim; Donggun An; Chulsoon Chang; Unhak Lim; Jiyeon Im; Wonju Sung; Hye-Ran Kim; et al. (IEEE J. Solid State Circuits, 2023)

Interface Engineering of Trench-Ox for Modern DRAM Devices. - Soojung Hwang; Jongkyu Kim; Juntae Kim; Dahyun Cha; Minho Kim; Dongkyu Jang; Sunghak Cho; Seokhyang Kim; Jaeseong Park; Hyungjoon Kim; Sukwon Yu; Boyoung Song; et al. (IRPS, 2024)

13.6 A 16Gb 37Gb/s GDDR7 DRAM with PAM3-Optimized TRX Equalization and ZQ Calibration. - Sung-Yong Cho; Moon-Chul Choi; Jaehyeok Baek; Donggun An; Sanghoon Kim; Daewoong Lee; Seongyeal Yang; Gil-Young Kang; Juseop Park; Kyungho Lee; Hwan-Chul Jung; Gun-hee Cho; et al. (ISSCC, 2024)

Study on the Measurement Method of Interface Resistance in HBM-DRAM: Novel Monitoring Method for Bump Contact Resistance. - Sanghyeon Jeon; Ilgeun Jung; Seungjin Kim; Sangki Kim; Yangkeun Park; Seungbum Kim; Boyoung Song; Hyodong Ban (IRPS, 2025)

A 16-Gb 37-Gb/s GDDR7 DRAM With PAM3-Optimized TRX Equalization and ZQ Calibration. - Sung-Yong Cho; Moon-Chul Choi; Jaehyeok Baek; Donggun An; Sang-Hoon Kim; Daewoong Lee; Seongyeal Yang; Se-Mi Kim; Gil-Young Kang; Juseop Park; Kyung-Ho Lee; Hwan-Chul Jung; et al. (IEEE J. Solid State Circuits, 2025)