Extraction of LRGC Matrices for 8-Coupled Uniform Lossy Transmission Lines Using 2-Port VNA Measurements. - Hyun Bae Lee; Kyoungho Lee; Hae Kang Jung; Hong June Park (IEICE Trans. Electron., 2006)

Mirrored Serpentine Microstrip Lines for Reduction of Far-End Crosstalk. - Hyun Bae Lee; Young-Chan Jang (IEICE Trans. Electron., 2012)

A 125MHz 64-Phase Delay-Locked Loop with Coarse-Locking Circuit Independent of Duty Cycle. - Pil-Ho Lee; Hyun Bae Lee; Young-Chan Jang (IEICE Trans. Electron., 2014)

An On-Chip Monitoring Circuit with 51-Phase PLL-Based Frequency Synthesizer for 8-Gb/s ODR Single-Ended Signaling Integrity Analysis. - Pil-Ho Lee; Yu-Jeong Hwang; Han-Yeol Lee; Hyun Bae Lee; Young-Chan Jang (IEICE Trans. Electron., 2016)

An On-Chip Monitoring Circuit for Signal-Integrity Analysis of 8-Gb/s Chip-to-Chip Interfaces With Source-Synchronous Clock. - Pil-Ho Lee; Han-Yeol Lee; Hyun Bae Lee; Young-Chan Jang (IEEE Trans. Very Large Scale Integr. Syst., 2017)

A 32-Gb/s PAM4-Binary Bridge With Sampler Offset Cancellation for Memory Testing. - Daeho Yun; Eonhui Lee; Woosong Jung; Kahyun Kim; Kyung-Min Beak; Jihee Kim; Hyun Bae Lee; Byeongseon Ko; Woo-Seok Choi; Deog-Kyoon Jeong (IEEE Trans. Circuits Syst. II Express Briefs, 2022)