Programmable and automatically adjustable on-die terminator for DDR3-SRAM interface. - Nam-Seog Kim; Yong-Jin Yoon; Uk-Rae Cho; Hyun-Geun Byun (CICC, 2003)

New dynamic logic-level converters for high performance application. - Nam-Seog Kim; Yong-Jin Yoon; Uk-Rae Cho; Hyun-Geun Byun (ISCAS (5), 2003)

A 1.2-V 1.5-Gb/s 72-Mb DDR3 SRAM. - Uk-Rae Cho; Tae-Hyoung Kim; Yong-Jin Yoon; Jong-Cheol Lee; Dae-Gi Bae; Nam-Seog Kim; Kang-Young Kim; Young-Jae Son; Jeong-Suk Yang; Kwon-Il Sohn; Sung-Tae Kim; In-Yeol Lee; et al. (IEEE J. Solid State Circuits, 2003)

Modeling and Testing of Faults in TCAMs. - Kwang-Jin Lee; Cheol Kim; Suki Kim; Uk-Rae Cho; Hyun-Geun Byun (AsiaSim, 2004)

Synchronous mirror delay for multiphase locking. - Yong-Jin Yoon; Hyuck In Kwon; Jong Duk Lee; Byung Gook Park; Nam-Seog Kim; Uk-Rae Cho; Hyun-Geun Byun (IEEE J. Solid State Circuits, 2004)

Low voltage wide range DLL-based quad-phase core clock generator for high speed network SRAM application. - Nam-Seog Kim; Uk-Rae Cho; Hyun-Geun Byun (CICC, 2005)

A pseudo-differential CMOS receiver insensitive to input common mode level. - Nam-Seog Kim; Uk-Rae Cho; Hyun-Geun Byun (ISCAS (1), 2005)

A 1.2V multi Gb/s/pin memory interface circuits with high linearity and low mismatch. - Tae-Hyoung Kim; Uk-Rae Cho; Hyun-Geun Byun (ISCAS (2), 2005)

A High Resolution, Wide Range Digital Impedance Controller. - Tae-Hyoung Kim; Kwang-Jin Lee; Uk-Rae Cho; Hyun-Geun Byun (IEICE Trans. Electron., 2005)

A Low Jitter ADPLL for Mobile Applications. - Kwang-Jin Lee; Hyo-Chang Kim; Uk-Rae Cho; Hyun-Geun Byun; Suki Kim (IEICE Trans. Electron., 2005)

A 0.18-μm 3.0-V 64-Mb nonvolatile phase-transition random access memory (PRAM). - Woo Yeong Cho; Beak-Hyung Cho; Byung-Gil Choi; Hyung-Rok Oh; Sangbeom Kang; Ki-Sung Kim; Kyung-Hee Kim; Du-Eung Kim; Choong-Keun Kwak; Hyun-Geun Byun; Youngnam Hwang; SuJin Ahn; et al. (IEEE J. Solid State Circuits, 2005)

A 0.1µm 1.8V 256Mb 66MHz Synchronous Burst PRAM. - Sangbeom Kang; WooYeong Cho; Beak-Hyung Cho; Kwangjin Lee; Changsoo Lee; Hyung-Rok Oh; Byung-Gil Choi; Qi Wang; Hye-Jin Kim; Mu-Hui Park; Yu-Hwan Ro; Suyeon Kim; et al. (ISSCC, 2006)

Enhanced write performance of a 64-mb phase-change random access memory. - Hyung-Rok Oh; Beak-Hyung Cho; Woo Yeong Cho; Sangbeom Kang; Byung-Gil Choi; Hye-Jin Kim; Ki-Sung Kim; Du-Eung Kim; Choong-Keun Kwak; Hyun-Geun Byun; Gitae Jeong; Hong-Sik Jeong; et al. (IEEE J. Solid State Circuits, 2006)

An autonomous SRAM with on-chip sensors in an 80-nm double stacked cell technology. - Kyomin Sohn; Hyun-Sun Mo; Young-Ho Suh; Hyun-Geun Byun; Hoi-Jun Yoo (IEEE J. Solid State Circuits, 2006)

A 0.1-µm 1.8-V 256-Mb Phase-Change Random Access Memory (PRAM) With 66-MHz Synchronous Burst-Read Operation. - Sangbeom Kang; Woo Yeong Cho; Beak-Hyung Cho; KwangJin Lee; Changsoo Lee; Hyung-Rok Oh; Byung-Gil Choi; Qi Wang; Hye-Jin Kim; Mu-Hui Park; Yu-Hwan Ro; Suyeon Kim; et al. (IEEE J. Solid State Circuits, 2007)

A 100nm Double-Stacked 500MHz 72Mb Separate-I/O Synchronous SRAM with Automatic Cell-Bias Scheme and Adaptive Block Redundancy. - Kyomin Sohn; Young-Ho Suh; Young-Jae Son; Daesik Yim; Kang-Young Kim; Dae-Gi Bae; Ted Kang; Hoon Lim; Soon-Moon Jung; Hyun-Geun Byun; Young-Hyun Jun; Kinam Kim (ISSCC, 2008)