A 250-Mbit/s CMOS crosspoint switch. - Hyun J. Shin; David A. Hodges (IEEE J. Solid State Circuits, 1989)

Performance comparison of driver configurations and full-swing techniques for BiCMOS logic circuits. - Hyun J. Shin (IEEE J. Solid State Circuits, 1990)

Full-swing BiCMOS logic circuits with complementary emitter-follower driver configuration. - Hyun J. Shin (IEEE J. Solid State Circuits, 1991)

A high-speed low-power JFET pull-down ECL circuit. - Hyun J. Shin; Pong-Fei Lu; Ching-Te Chuang (IEEE J. Solid State Circuits, 1991)

High-speed low-power ECL circuit with AC-coupled self-biased dynamic current source and active-pull-down emitter-follower stage. - Ching-Te Chuang; Kenneth Chin; Hyun J. Shin; Pong-Fei Lu (IEEE J. Solid State Circuits, 1992)

An experimental 5-Gb/s 16*16 Si-bipolar crosspoint switch. - Hyun J. Shin; Michael Immediato (IEEE J. Solid State Circuits, 1992)

High-speed low-power Darlington ECL circuit. - Ching-Te Chuang; Kenneth Chin; Pong-Fei Lu; Hyun J. Shin (IEEE J. Solid State Circuits, 1993)

A self-biased feedback-controlled pull-down emitter follower for high-speed low-power bipolar logic circuits. - Hyun J. Shin (IEEE J. Solid State Circuits, 1994)

Custom design of CMOS low-power high-performance digital signal-processing macro for hard-disk-drive applications. - Hyun J. Shin; Dale J. Pearson; Scott K. Reynolds; Andrew C. Megdanis; Sudhir M. Gowda; Kevin R. Wrenner (IBM J. Res. Dev., 1995)

Digital FIR filters for high speed PRML disk read channels. - Dale J. Pearson; Scott K. Reynolds; Andrew C. Megdanis; Sudhir M. Gowda; Kevin R. Wrenner; Michael Immediato; Richard L. Galbraith; Hyun J. Shin (IEEE J. Solid State Circuits, 1995)

Single-chip 4×500-MBd CMOS transceiver. - Albert X. Widmer; Kevin R. Wrenner; Herschel A. Ainspan; Ben Parker; Pierre Austruy; Bernard Brezzo; Anne-Marie Haen; John F. Ewen; Mehmet Soyuer; Alain Blanc; Jean-Claude Abbiate; Alina Deutsch; et al. (IEEE J. Solid State Circuits, 1996)

Source-synchronization and timing vernier techniques for 1.2-GB/s SLDRAM interface. - Yasunobu Nakase; Yoshikazu Morooka; David J. Perlman; Daniel J. Kolor; Jae-Myoung Choi; Hyun J. Shin; Tsutomu Yoshimura; Naoya Watanabe; Yoshio Matsuda; Masaki Kumanoya; Michihiro Yamada (IEEE J. Solid State Circuits, 1999)

A quad 0.6-3.2 Gb/s/channel interference-free CMOS transceiver for backplane serial link. - Yongsam Moon; Young-Soo Park; Namhoon Kim; Gijung Ahn; Hyun J. Shin; Deog-Kyoon Jeong (IEEE J. Solid State Circuits, 2004)