A process and environment tolerant 3V, 2 GHz VCO with 0.8 μm CMOS technology. - Keewook Jung; Changsik Yoo; Hyun-Kyu Yu; Wonchui Song; Wonchan Kim (IEEE Trans. Consumer Electron., 1999)

A gain boosting method at RF frequency using active feedback and its application to RF variable gain amplifier (VGA). - Kwang-Jin Koh; Yong-Sik Youn; Hyun-Kyu Yu (ISCAS (3), 2002)

A high speed direct digital frequency synthesizer using a low power pipelined parallel accumulator. - Byung-Do Yang; Lee-Sup Kim; Hyun-Kyu Yu (ISCAS (5), 2002)

A 1.8V triode-type transconductor and its application to a 10MHz 3rd-order Chebyshev low pass filter. - Young-Ho Kim; Jung-Woo Park; Mun-Yang Park; Hyun-Kyu Yu (CICC, 2004)

Subharmonically pumped CMOS frequency conversion (up and down) circuits for 2-GHz WCDMA direct-conversion transceiver. - Kwang-Jin Koh; Mun-Yang Park; Cheon-Soo Kim; Hyun-Kyu Yu (IEEE J. Solid State Circuits, 2004)

An 800-MHz low-power direct digital frequency synthesizer with an on-chip D/a converter. - Byung-Do Yang; Jang-Hong Choi; Seon-Ho Han; Lee-Sup Kim; Hyun-Kyu Yu (IEEE J. Solid State Circuits, 2004)

Automatic tuning circuit for Gm-C filters. - Young-Ho Kim; Hyun-Kyu Yu (ICECS, 2005)

A transformer-based low phase noise and widely tuned CMOS quadrature VCO. - Young-Jae Lee; Hyun-Kyu Yu (ISCAS, 2006)

A 10Gb/s CMOS CDR and DEMUX IC with a Quarter-Rate Linear Phase Detector. - Sangjin Byun; Jyung Chan Lee; Jae Hoon Shim; Kwangjoon Kim; Hyun-Kyu Yu (ISSCC, 2006)

A 20gb/s 1: 4 DEMUX without inductors in 0.13µm CMOS. - Byung-Guk Kim; Lee-Sup Kim; Sangjin Byun; Hyun-Kyu Yu (ISSCC, 2006)

A 10-Gb/s CMOS CDR and DEMUX IC With a Quarter-Rate Linear Phase Detector. - Sangjin Byun; Jyung Chan Lee; Jae Hoon Shim; Kwangjoon Kim; Hyun-Kyu Yu (IEEE J. Solid State Circuits, 2006)

A 20 Gb/s 1: 4 DEMUX Without Inductors and Low-Power Divide-by-2 Circuit in 0.13 µm CMOS Technology. - Byung-Guk Kim; Lee-Sup Kim; Sangjin Byun; Hyun-Kyu Yu (IEEE J. Solid State Circuits, 2008)

A low power discrete-time receiver for triple-band FM/T-DMB/DAB system-on-chip. - Hoai-Nam Nguyen; Seung-Hwan Jung; Byung-Hun Min; Young-Jae Lee; Sang-Gug Lee 001; Yun Seong Eo; Hyun-Kyu Yu (ESSCIRC, 2011)

A digital-intensive receiver front-end using VCO-based ADC with an embedded 2nd-Order anti-aliasing Sinc filter in 90nm CMOS. - Jaewook Kim; Wonsik Yu; Hyun-Kyu Yu; SeongHwan Cho (ISSCC, 2011)

A 4-GHz All Digital PLL With Low-Power TDC and Phase-Error Compensation. - Ja-Yol Lee; Mi-Jeong Park; Byung-Hun Min; Seongdo Kim; Mun-Yang Park; Hyun-Kyu Yu (IEEE Trans. Circuits Syst. I Regul. Pap., 2012)

1-5.6 Gb/s CMOS clock and data recovery IC with a static phase offset compensated linear phase detector. - Sangjin Byun; Chung Hwan Son; Jongil Hwang; Byung-Hun Min; Mun-Yang Park; Hyun-Kyu Yu (IET Circuits Devices Syst., 2013)

A 230ns settling time type-I PLL with 0.96mW TDC power and simple TV calculation algorithm. - Ja-Yol Lee; Mi-Jeong Park; Hyun-Kyu Yu; Cheon-Soo Kim (MWSCAS, 2014)