Level 1 & Victim Cache Management with Processor Reuse Information. - Jong Wook Kwak; Hyunbae Lee; Cheol Hong Kim; Sung-Hoon Shim; Chu Shik Jhon (PDPTA, 2004)

A 27% reduction in transceiver power for single-ended point-to-point DRAM interface with the termination resistance of 4×Z0 at both TX and RX. - Soo-Min Lee; Jong-Hoon Kim; Jong-Sam Kim; Yunsaing Kim; Hyunbae Lee; Jae-Yoon Sim; Hong-June Park (ISSCC, 2013)

A 16.8Gbps/channel single-ended transceiver in 65nm CMOS for SiP based DRAM interface on Si-carrier channel. - Hyunbae Lee; Taeksang Song; Sangyeon Byeon; Kwanghun Lee; Inhwa Jung; Seongjin Kang; Ohkyu Kwon; Koeun Cheon; Donghwan Seol; Jong-Ho Kang; Gunwoo Park; Yunsaing Kim (A-SSCC, 2014)

An 80 mV-Swing Single-Ended Duobinary Transceiver With a TIA RX Termination for the Point-to-Point DRAM Interface. - Soo-Min Lee; Il-Min Yi; Hae-Kang Jung; Hyunbae Lee; Yong-Ju Kim; Yunsaing Kim; Byungsub Kim; Jae-Yoon Sim; Hong-June Park (IEEE J. Solid State Circuits, 2014)

A 16.8 Gbps/Channel Single-Ended Transceiver in 65 nm CMOS for SiP-Based DRAM Interface on Si-Carrier Channel. - Hyunbae Lee; Taeksang Song; Sangyeon Byeon; Kwanghun Lee; Inhwa Jung; Seongjin Kang; Ohkyu Kwon; Koeun Cheon; Donghwan Seol; Jong-Ho Kang; Gunwoo Park; Yunsaing Kim (IEEE J. Solid State Circuits, 2015)

A Delay Locked Loop With a Feedback Edge Combiner of Duty-Cycle Corrector With a 20%-80% Input Duty Cycle for SDRAMs. - Ji-Hoon Lim; Jun-Hyun Bae; Jaemin Jang; Hae-Kang Jung; Hyunbae Lee; Yongju Kim; Byungsub Kim; Jae-Yoon Sim; Hong-June Park (IEEE Trans. Circuits Syst. II Express Briefs, 2016)

A 12-b 2 MS/s R-C Two-Step SAR ADC with Bit-Cycling Time Control and LSB Correction Logic. - Hyeokjoon Yang; Hyunbae Lee; Hanseul Kim; Sangwook Park; Jinwook Burm (ISOCC, 2020)

All-digital half-rate referenceless CDR with single direction frequency sweep scheme using asymmetric binary phase detector. - Changzhi Yu; Himchan Park; Qiwei Huang; Daewung Lee; Hyunmook Kim; Hyunbae Lee; Jinwook Burm (IEICE Electron. Express, 2020)