A 16Gb LPDDR4X SDRAM with an NBTI-tolerant circuit solution, an SWD PMOS GIDL reduction technique, an adaptive gear-down scheme and a metastable-free DQS aligner in a 10nm class DRAM process. - Ki Chul Chun; Yonggyu Chu; Jin-Seok Heo; Tae-Sung Kim; Soohwan Kim; Hui-Kap Yang; Mi-Jo Kim; Chang-Kyo Lee; Ju-Hwan Kim; Hyunchul Yoon; Chang-Ho Shin; Sang-uhn Cha; et al. (ISSCC, 2018)

A 50 MS/s 65 dB-SNDR Pipelined SAR ADC using Capacitively Degenerated Two-Stage Dynamic Amplifier. - Hyunchul Yoon; Teawoong Kim; Yigi Kwon; Youngcheol Chae (VLSI Technology and Circuits, 2022)

An 11bit 360MS/s Pipelined SAR ADC with Dynamic Negative-C Assisted Residue Amplifier. - Yigi Kwon; Sangwoo Lee; Changuk Lee; Hyunchul Yoon; Byounghan Min; Youngcheol Chae (A-SSCC, 2023)

A 65-dB-SNDR Pipelined SAR ADC Using PVT-Robust Capacitively Degenerated Dynamic Amplifier. - Hyunchul Yoon; Changuk Lee; Taewoong Kim; Yigi Kwon; Youngcheol Chae (IEEE J. Solid State Circuits, 2023)

A Single-Ended Offset-Compensating Bit-Line Sense-Amplifier with Ground Precharge and Charge Transfer Pre sensing for Sub-1V DRAM. - Changyoung Lee; Youngseok Park; Hyunchul Yoon; Seryeong Yoon; Donggeon Kim; Bokyeon Won; Junhwa Song; In-Jae Bae; Jaejoon Song; Kyuchang Kang; Jaehyuk Kim; Kyungrak Cho; et al. (A-SSCC, 2024)

An Offset-Compensated Charge-Transfer Pre-Sensing Bit-Line Sense-Amplifier for Low-Voltage DRAM. - Kyeongtae Nam; Jaehyuk Kim; Dongil Lee; Kyuchang Kang; Sangyun Kim; Changyoung Lee; Hyunchul Yoon; Donggeon Kim; Bokyeon Won; Jaejoon Song; Incheol Nam; Young-Hun Seo; et al. (VLSI Technology and Circuits, 2024)

An Offset Compensated Charge Transfer Pre-Sensing Bitline Sense Amplifier. - Kyeongtae Nam; Dongil Lee; Kyuchang Kang; Sangyun Kim; Changyoung Lee; Hyunchul Yoon; Donggeon Kim; Bokyeon Won; Jaejoon Song; Jaehyuk Kim; Incheol Nam; Young-Hun Seo; et al. (IEEE J. Solid State Circuits, 2025)