Structural and Device Considerations for Vertical Cross Point Memory with Single-stack Memory toward CXL Memory beyond 1x nm 3DXP. - Sijung Yoo; Donghoon Kim; Yoon Mo Koo; Sujee Kim Wooju Jeong; Hyungjoon Shim; Won-Jun Lee; Beom Seok Lee; Seungyun Lee; Hyejung Choi; Hyung Dong Lee; Taehoon Kim; Myung-Hee Na (IMW, 2022)

Modeling and Demonstration for Multi-level Weight Conductance in Computational FeFET Memory Cell. - Won-Tae Koo; Jae-Gil Lee; Gunhee Lee; Woocheol Lee; Jungwook Woo; Dong Ik Suh; Joongsik Kim; Hyung Dong Lee; Seho Lee; Jaeyun Yi; Seonyong Cha (IMW, 2024)

Improvement of MAC Accuracy using Oxygen Diffusion Barriers in Resistive Synaptic Cell Arrays. - Youngjae Kwon; Won-Tae Koo; Sangsu Park; Dong Ik Suh; Gunhee Lee; Hyung Dong Lee; Youngbae Ahn; Dohee Kim; Seungwook Ryu; Hoseok Em; Seokjoon Kang; Chang Won Jeong; et al. (IMW, 2024)

First Demonstration of Fully Integrated 16 nm Half-Pitch Selector Only Memory (SOM) for Emerging CXL Memory. - Myoungsub Kim; Yooncheol Bae; Jaehyuk Park; Jeongho Yeon; Hyungjoon Shim; Sehyun Jin; Hyunsoo Kim; Sangchul Oh; Gapsok Do; Dongyeol Yun; Hyung Dong Lee; David Ahn; et al. (VLSI Technology and Circuits, 2024)