A VCDL-based 60-760-MHz dual-loop DLL with infinite phase-shift capability and adaptive-bandwidth scheme. - Seung-Jun Bae; Hyung-Joon Chi; Young-Soo Sohn; Hong-June Park (IEEE J. Solid State Circuits, 2005)

A 3.2Gb/s 8b Single-Ended Integrating DFE RX for 2-Drop DRAM Interface with Internal Reference Voltage and Digital Calibration. - Hyung-Joon Chi; Jae-Seung Lee; Seong-Hwan Jeon; Seung-Jun Bae; Jae-Yoon Sim; Hong-June Park (ISSCC, 2008)

A 2-Gb/s CMOS Integrating Two-Tap DFE Receiver for Four-Drop Single-Ended Signaling. - Seung-Jun Bae; Hyung-Joon Chi; Young-Soo Sohn; Jae-Seung Lee; Jae-Yoon Sim; Hong-June Park (IEEE Trans. Circuits Syst. I Regul. Pap., 2009)

A Single-Loop SS-LMS Algorithm With Single-Ended Integrating DFE Receiver for Multi-Drop DRAM Interface. - Hyung-Joon Chi; Jae-Seung Lee; Seong-Hwan Jeon; Seung-Jun Bae; Young-Soo Sohn; Jae-Yoon Sim; Hong-June Park (IEEE J. Solid State Circuits, 2011)

A 2-Gb/s Intrapanel Interface for TFT-LCD With a VSYNC-Embedded Subpixel Clock and a Cascaded Deskew and Multiphase DLL. - Hyung-Joon Chi; Young-Ho Choi; Soo-Min Lee; Jae-Yoon Sim; Hong-June Park; Jong-Jin Lim; Pil-Sung Kang; Bu-Yeol Lee; Jin-Cheol Hong; Hee-Sub Lee (IEEE Trans. Circuits Syst. II Express Briefs, 2011)

A 7.5Gb/s/pin LPDDR5 SDRAM With WCK Clocking and Non-Target ODT for High Speed and With DVFS, Internal Data Copy, and Deep-Sleep Mode for Low Power. - Kyung-Soo Ha; Chang-Kyo Lee; Dongkeon Lee; Daesik Moon; Jin-Hun Jang; Hyong-Ryol Hwang; Hyung-Joon Chi; Junghwan Park; Seungjun Shin; Dukha Park; Sang-Yun Kim 001; Sukhyun Lim; et al. (ISSCC, 2019)

22.2 An 8.5Gb/s/pin 12Gb-LPDDR5 SDRAM with a Hybrid-Bank Architecture using Skew-Tolerant, Low-Power and Speed-Boosting Techniques in a 2nd generation 10nm DRAM Process. - Hyung-Joon Chi; Chang-Kyo Lee; Junghwan Park; Jin-Seok Heo; Jaehoon Jung; Dongkeon Lee; Dae-Hyun Kim 003; Dukha Park; Kihan Kim; Sang-Yun Kim 001; Jinsol Park; Hyunyoon Cho; et al. (ISSCC, 2020)

An 8.5-Gb/s/Pin 12-Gb LPDDR5 SDRAM With a Hybrid-Bank Architecture, Low Power, and Speed-Boosting Techniques. - Chang-Kyo Lee; Hyung-Joon Chi; Jin-Seok Heo; Junghwan Park; Jin-Hun Jang; Dongkeon Lee; Jaehoon Jung; Dong-Hun Lee; Dae-Hyun Kim 003; Kihan Kim; Sang-Yun Kim 001; Dukha Park; et al. (IEEE J. Solid State Circuits, 2021)