A 500-Mb/s quadruple data rate SDRAM interface using a skew cancellation technique. - Sung-Ho Wang; Jeongpyo Kim; Joonsuk Lee; Hyoung Sik Nam; Young Gon Kim; Jae Hoon Shim; Hyung Ki Ahn; Seok Kang; Bong Hwa Jeong; Jin-Hong Ahn; Beomsup Kim (IEEE J. Solid State Circuits, 2001)

A 5-GHz self-calibrated I/Q clock generator using a quadrature LC-VCO. - Hyung Ki Ahn; In-Cheol Park; Beomsup Kim (ISCAS (1), 2003)

A ΔΣ Fractional-N Synthesizer With Customized Noise Shaping for WCDMA/HSDPA Applications. - Xueyi Yu; Yuanfeng Sun; Woogeun Rhee; Hyung Ki Ahn; Byeong-Ha Park; Zhihua Wang 001 (IEEE J. Solid State Circuits, 2009)