Test Generation of Stuck-open Faults Using Stuck-at Test Sets in CMOS Combinational Circuits. - Hyung Ki Lee; Dong Sam Ha; Kwanghyun Kim (DAC, 1989)

SOPRANO: An Efficient Automatic Test Pattern Generator for Stuck-Open Faults in CMOS Combinational Circuits. - Hyung Ki Lee; Dong Sam Ha (DAC, 1990)

An Efficient, Forward Fault Simulation Algorithm Based on the Parallel Pattern Single Fault Propagation. - Hyung Ki Lee; Dong Sam Ha (ITC, 1991)

Comments on 'A method of fault simulation based on stem regions'. - Hyung Ki Lee; Dong S. Ha 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1992)

New methods of improving parallel fault simulation in synchronous sequential circuits. - Hyung Ki Lee; Dong Sam Ha (ICCAD, 1993)

Fault simulation and test pattern generation for synchronous and asynchronous sequential circuits. - Hyung Ki Lee (1993)

An Efficient Automatic Test Pattern Generator for Stuck-Open Faults in CMOS Combinational Circuits. - Hyung Ki Lee; Dong S. Ha 001 (VLSI Design, 1994)

HOPE: an efficient parallel fault simulator for synchronous sequential circuits. - Hyung Ki Lee; Dong Sam Ha (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996)

NDIS-based virtual polling algorithm for IEEE 802.11b for guaranteeing the real-time requirements. - Suk Lee; Kyoung Nam Ha; Ji Hoon Park; Kyung Chang Lee; Gi Sig Byun; Hyung Ki Lee (Comput. Stand. Interfaces, 2007)