A high speed and low power SOL inverter using active body-bias. - Joonho Gil; Minkyu Je; Jongho Lee; Hyungcheol Shin (ISLPED, 1998)

A simple four-terminal small-signal model of RF MOSFETs and its parameter extraction. - Minkyu Je; Jeonghu Han; Hyungcheol Shin; Kwyro Lee (Microelectron. Reliab., 2003)

Complete high-frequency thermal noise modeling of short-channel MOSFETs and design of 5.2-GHz low noise amplifier. - Kwangseok Han; Joonho Gil; Seong-Sik Song; Jeonghu Han; Hyungcheol Shin; Choong-Ki Kim; Kwyro Lee (IEEE J. Solid State Circuits, 2005)

Analyses on Current Characteristics of 3-D MOSFET Determined by Junction Doping Profiles for Nonvolatile Memory Devices. - Seongjae Cho; Jang-Gn Yun; Il-Han Park; Jung Hoon Lee; Jong Pil Kim; Jong Duk Lee; Hyungcheol Shin; Byung-Gook Park (IEICE Trans. Electron., 2007)

Accurate Extraction of the Trap Depth from RTS Noise Data by Including Poly Depletion Effect and Surface Potential Variation in MOSFETs. - Hochul Lee; Youngchang Yoon; Seongjae Cho; Hyungcheol Shin (IEICE Trans. Electron., 2007)

Establishing Read Operation Bias Schemes for 3-D Pillar Structure Flash Memory Devices to Overcome Paired Cell Interference (PCI). - Seongjae Cho; Il-Han Park; Jung Hoon Lee; Jang-Gn Yun; Doo-Hyun Kim; Jong Duk Lee; Hyungcheol Shin; Byung-Gook Park (IEICE Trans. Electron., 2008)

FN Stress Induced Degradation on Random Telegraph Signal Noise in Deep Submicron NMOSFETs. - Hochul Lee; Youngchang Yoon; Ickhyun Song; Hyungcheol Shin (IEICE Trans. Electron., 2008)

Design Consideration for Vertical Nonvolatile Memory Device Regarding Gate-Induced Barrier Lowering (GIBL). - Seongjae Cho; Jung Hoon Lee; Gil Sung Lee; Jong Duk Lee; Hyungcheol Shin; Byung-Gook Park (IEICE Trans. Electron., 2009)

Application of the Compact Channel Thermal Noise Model of Short Channel MOSFETs to CMOS RFIC Design. - Jongwook Jeon; Ickhyun Song; Jong Duk Lee; Byung-Gook Park; Hyungcheol Shin (IEICE Trans. Electron., 2009)

3-Dimensional Terraced NAND (3D TNAND) Flash Memory-Stacked Version of Folded NAND Array. - Yoon Kim; Seongjae Cho; Gil Sung Lee; Il-Han Park; Jong Duk Lee; Hyungcheol Shin; Byung-Gook Park (IEICE Trans. Electron., 2009)

Simulation of Retention Characteristics in Double-Gate Structure Multi-Bit SONOS Flash Memory. - Doo-Hyun Kim; Il-Han Park; Seongjae Cho; Jong Duk Lee; Hyungcheol Shin; Byung-Gook Park (IEICE Trans. Electron., 2009)

Simulation Study on Dependence of Channel Potential Self-Boosting on Device Scale and Doping Concentration in 2-D and 3-D NAND-Type Flash Memory Devices. - Seongjae Cho; Jung Hoon Lee; Yoon Kim; Jang-Gn Yun; Hyungcheol Shin; Byung-Gook Park (IEICE Trans. Electron., 2010)

The novel SCR-based ESD protection with low triggering and high holding voltages. - Myounggon Kang; Ki-Whan Song; Byung-Gook Park; Hyungcheol Shin (Microelectron. J., 2011)

A 55dB SNR with 240Hz frame scan rate mutual capacitor 30×24 touch-screen panel read-out IC using code-division multiple sensing technique. - Hyungcheol Shin; Seunghoon Ko; Hongjae Jang; Ilhyun Yun; Kwyro Lee (ISSCC, 2013)

L-Shaped Tunneling Field-Effect Transistors for Complementary Logic Applications. - Sang Wan Kim; Woo Young Choi; Min-Chul Sun; Hyun Woo Kim 005; Jong-Ho Lee 002; Hyungcheol Shin; Byung-Gook Park (IEICE Trans. Electron., 2013)

Analysis of failure mechanisms in erased state of sub 20-nm NAND Flash memory. - Kyunghwan Lee; Duckseoung Kang; Hyungcheol Shin; Sangjin Kwon; Shinhyung Kim; Yuchul Hwang (ESSDERC, 2014)

12.5 2D Coded-aperture-based ultra-compact capacitive touch-screen controller with 40 reconfigurable channels. - Hongjae Jang; Hyungcheol Shin; Seunghoon Ko; Ilhyun Yun; Kwyro Lee (ISSCC, 2014)

Analysis and modeling for random telegraph noise of GIDL current in saddle MOSFET for DRAM application. - Dyukyoung Moon; Hyunseul Lee; Changhwan Shin; Hyungcheol Shin (IEICE Electron. Express, 2014)

Tactile Tone System: A Wearable Device to Assist Accuracy of Vocal Pitch in Cochlear Implant Users. - Sungyong Shin; Changmok Oh; Hyungcheol Shin (ASSETS, 2020)

Modeling of Charge Failure Mechanisms during the Short Term Retention Depending on Program/Erase Cycle Counts in 3-D NAND Flash Memories. - Changbeom Woo; Shinkeun Kim; Jaeyeol Park; Hyungcheol Shin; Haesoo Kim; Gil-Bok Choi; Moon-Sik Seo; Keum Hwan Noh (IRPS, 2020)

28.2 A 51dB-SNR 120Hz-Scan-Rate 32×18 Segmented-VCOM LCD In-Cell Touch-Display-Driver IC with 96-Channel Compact Shunt-Sensing Self-Capacitance Analog Front-End. - Hongjae Jang; Hyungcheol Shin; Jaemin Lee; Changwon Yoo; Kanghyup Chun; Ilhyun Yun (ISSCC, 2020)

Machine learning model for predicting threshold voltage by taper angle variation and word line position in 3D NAND flash memory. - Dong Chan Lee; Jang Kyu Lee; Hyungcheol Shin (IEICE Electron. Express, 2020)

Transient program operation model considering distribution of electrons in 3D NAND flash memories. - Dong Chan Lee; Hyungcheol Shin (IEICE Electron. Express, 2020)

A Simple and Accurate Modeling Method of Channel Thermal Noise Using BSIM4 Noise Models. - Ilho Myeong; Juhyun Kim; Hyungwoo Ko; Ickhyun Song; Yongseok Kim; Hyungcheol Shin (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

Optimizing read disturb phenomenon with new read scheme by partial-boosting channel in 3-D NAND Flash memories. - Sangmin Ahn; Hyungcheol Shin (IEICE Electron. Express, 2021)

Investigation of endurance degradation for 3-D charge trap NAND flash memory with bandgap-engineered tunneling oxide. - Jongwoo Kim; Hyungjun Jo; Yonggyu Cho; Hyunyoung Shim; Jaesung Sim; Hyungcheol Shin (IEICE Electron. Express, 2022)

A Novel Read Scheme Using GIDL Current to Suppress Read Disturbance in 3-D nand Flash Memories. - Hyungjun Jo; Jongwoo Kim; Hyungcheol Shin (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

Modeling of Threshold Voltage Shift by Neighboring Transistors for Macaroni Channel MOSFETs in Series. - Quan Nguyen-Gia; Hyungcheol Shin (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)