A Scalable and Parallel Test Access Strategy for NoC-Based Multicore System. - Taewoo Han; Inhyuk Choi; Hyunggoy Oh; Sungho Kang 001 (ATS, 2014)

Test access mechaism for stack test time reduction of 3-dimensional integrated circuit. - Inhyuk Choi; Hyunggoy Oh; Sungho Kang 001 (APCCAS, 2016)

A new online test and debug methodology for automotive camera image processing system. - Hyunggoy Oh; Inhyuk Choi; Sungho Kang 001 (APCCAS, 2016)

Process variation-aware bridge fault analysis. - Heetae Kim; Inhyuk Choi; Jaeil Lim; Hyunggoy Oh; Sungho Kang 001 (ISOCC, 2016)

Parallelized Network-on-Chip-Reused Test Access Mechanism for Multiple Identical Cores. - Taewoo Han; Inhyuk Choi; Hyunggoy Oh; Sungho Kang 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016)

A selective error data capture method using on-chip DRAM for silicon debug of multi-core design. - Hyunggoy Oh; Heetae Kim; Jaeil Lim; Sungho Kang 001 (ISOCC, 2017)

A novel X-filling method for capture power reduction. - Heetae Kim; Hyunggoy Oh; Jaeil Lim; Sungho Kang 001 (IEICE Electron. Express, 2017)

Reconfigurable scan architecture for test power and data volume reduction. - Hyunggoy Oh; Heetae Kim; Jaeil Lim; Sungho Kang 001 (IEICE Electron. Express, 2017)

Proof of Concept of Home IoT Connected Vehicles. - Younsun Kim; Hyunggoy Oh; Sungho Kang 001 (Sensors, 2017)

DRAM-Based Error Detection Method to Reduce the Post-Silicon Debug Time for Multiple Identical Cores. - Hyunggoy Oh; Inhyuk Choi; Sungho Kang 001 (IEEE Trans. Computers, 2017)

An On-Chip Error Detection Method to Reduce the Post-Silicon Debug Time. - Hyunggoy Oh; Taewoo Han; Inhyuk Choi; Sungho Kang 001 (IEEE Trans. Computers, 2017)

Low Power Scan Chain Architecture Based on Circuit Topology. - Heetae Kim; Hyunggoy Oh; Sangjun Lee; Sungho Kang 001 (ISOCC, 2018)

Dynamic voltage Drop induced Path Delay Analysis for STV and NTV Circuits during At-speed Scan Test. - Hyunggoy Oh; Heetae Kim; Sangjun Lee; Sungho Kang 001 (ISOCC, 2018)

Test Resource Reused Debug Scheme to Reduce the Post-Silicon Debug Cost. - Inhyuk Choi; Hyunggoy Oh; Young-Woo Lee; Sungho Kang 001 (IEEE Trans. Computers, 2018)

Thermal Aware Test Scheduling for NTV Circuit. - Jaeil Lim; Hyunggoy Oh; Heetae Kim; Sungho Kang 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018)

A New Scan Chain Reordering Method for Low Power Consumption based on Care Bit Density. - Kyunghwan Cho; Jihye Kim 002; Hyunggoy Oh; Sangjun Lee; Sungho Kang 001 (ISOCC, 2019)

On-Chip Error Detection Reusing Built-In Self-Repair for Silicon Debug. - Hayoung Lee; Hyunggoy Oh; Sungho Kang 001 (IEEE Access, 2021)