A noise-immune stylus analog front-end using adjustable frequency modulation and linear-interpolating data reconstruction for both electrically coupled resonance and active styluses. - Kyung-Hoon Lee; Sang-Pil Nam; Jung-Ho Lee; Michael Choi; Hyungjong Ko; San-Ho Byun; Jin-chul Lee; Yong-Hoon Lee; Yeong-Cheol Rhee; Yoon-Kyung Choi; Byunghoon Kang; Changbyung Park; et al. (ISSCC, 2018)

A 4.2-mW 10-MHz BW 74.4-dB SNDR Continuous-Time Delta-Sigma Modulator With SAR-Assisted Digital-Domain Noise Coupling. - Il-Hoon Jang; Min-Jae Seo; Sang-Hyun Cho; Jae-Keun Lee; Seung-Yeob Baek 002; Sunwoo Kwon; Michael Choi; Hyungjong Ko; Seung-Tak Ryu (IEEE J. Solid State Circuits, 2018)

An 8nm All-Digital 7.3Gb/s/pin LPDDR5 PHY with an Approximate Delay Compensation Scheme. - Kwanyeob Chae; JongRyun Choi; Hyungkwon Lee; Jinho Choi; Shinyoung Yi 002; Yoonjee Nam; Sangyun Hwang; Joohyung Lee; Won Lee; Kihwan Seong; Joohee Shin; Soo-Min Lee; et al. (VLSI Circuits, 2019)

A 9.1-ENOB 6-mW 10-Bit 500-MS/s Pipelined-SAR ADC With Current-Mode Residue Processing in 28-nm CMOS. - Kyoung-Jun Moon; Dong-Shin Jo; Wan Kim; Michael Choi; Hyungjong Ko; Seung-Tak Ryu (IEEE J. Solid State Circuits, 2019)

20.3 A 4.0×3.7×1.0mm3-MEMS CMOS Integrated E-Nose with Embedded 4×Gas Sensors, a Temperature Sensor and a Relative Humidity Sensor. - Si Hoon Lee; Kwangmin Park; Jaeheung Lim; Minchul Lee; Jeongho Park; Hyun Kim; Young Ok Lee; Hyun Su Ahn; Eunseok Shin; Hyungjong Ko; Seoung-Jae Yoo; Hyunsurk Ryu; et al. (ISSCC, 2020)

A 24Gb/s/pin PAM-4 Built Out Tester chip enabling PAM-4 chips test with NRZ interface ATE. - Hyungmin Jin; Jindo Byun; Hyunyoon Cho; Hojun Yoon; Jin-Hee Park; Kyoungsoo Kim; Youngdon Choi; Jung-Hwan Choi; Hyungjong Ko; Sang-Hyun Lee (A-SSCC, 2021)

A 3.2-12.8Gb/s Duty-Cycle Compensating Quadrature Error Corrector for DRAM Interfaces, With Fast Locking and Low Power Characteristics. - Hojun Yoon; Wonjoo Jung; Jaewoo Park; Jindo Byun; Hyungmin Jin; Hyunyoon Cho; Youngmin Kim; Baek-Jin Lim; Young-Chul Cho; Youngdon Choi; Jung-Hwan Choi; Hyungjong Ko; et al. (ESSCIRC, 2021)

A 60-Gb/s/pin single-ended PAM-4 transmitter with timing skew training and low power data encoding in mimicked 10nm class DRAM process. - Joohwan Kim; Junyoung Park; Jindo Byun; Changkyu Seol; Chang Soo Yoon; EunSeok Shin; Hyunyoon Cho; Youngdo Um; Sucheol Lee; Hyungmin Jin; Kwangseob Shin; Hyunsub Norbert Rie; et al. (CICC, 2022)

A 16Gb 27Gb/s/pin T-coil based GDDR6 DRAM with Merged-MUX TX, Optimized WCK Operation, and Alternative-Data-Bus. - Daewoong Lee; Hye-Jung Kwon; Daehyun Kwon; Jaehyeok Baek; Chulhee Cho; Sanghoon Kim; Donggun An; Chulsoon Chang; Unhak Lim; Jiyeon Im; Wonju Sung; Hye-Ran Kim; et al. (ISSCC, 2022)

A 40-Gb/s/pin Low-Voltage POD Single-Ended PAM-4 Transceiver with Timing Calibrated Reset-less Slicer and Bidirectional T-Coil for GDDR7 Application. - Hyunsub Norbert Rie; Chang Soo Yoon; Jindo Byun; Sucheol Lee; Garam Kim; Joohwan Kim; Junyoung Park; Hyunyoon Cho; Youngdo Um; Hyungmin Jin; Kwangseob Shin; Minsu Jung; et al. (VLSI Technology and Circuits, 2022)

A 4ns Settling Time FVF-Based Fast LDO Using Bandwidth Extension Techniques for HBM3. - Jinook Jung; Jun-Han Choi; Kyoung-Jun Roh; Jaewoo Park; Won-Mook Lim; Tae-Sung Kim; Han-Ki Jeong; Myoungbo Kwak; Jaeyoun Youn; Jeong-Don Ihm; Changsik Yoo; Youngdon Choi; et al. (A-SSCC, 2023)

A 16-Gb T-Coil-Based GDDR6 DRAM With Merged-MUX TX, Optimized WCK Operation, and Alternative-Data-Bus Achieving 27-Gb/s/Pin in NRZ. - Daewoong Lee; Jaehyeok Baek; Hye-Jung Kwon; Daehyun Kwon; Chulhee Cho; Sang-Hoon Kim; Donggun An; Chulsoon Chang; Unhak Lim; Jiyeon Im; Wonju Sung; Hye-Ran Kim; et al. (IEEE J. Solid State Circuits, 2023)

A 12-Gb/s Baud-Rate Clock and Data Recovery With 75% Phase-Detection Probability by Precoding and Integration-Hold-Reset Frontend. - Hyeongmin Seo; Jiyun Han; Kyungmin Kim 003; Baek-Jin Lim; EunSeok Shin; Youngdon Choi; Hyungjong Ko; Jung-Hwan Choi; Sang-Hyun Lee; Changsik Yoo; Jaeduk Han (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

A 20Gb/s/pin Single-Ended PAM-4 Transceiver with Pre/Post-Channel Switching Jitter Compensation and DQS-Driven Biasing for Low-Power Memory Interfaces. - Kyunghwan Min; Jahoon Jin; Soo-Min Lee; Sodam Ju; Jisu Yook; Jihoon Lee; Yunji Hong; Sungsik Park; Sang-Ho Kim; Jongwoo Lee; Hyungjong Ko (VLSI Technology and Circuits, 2024)

A 4 ns Settling Time FVF-Based Fast LDO Using Bandwidth Extension Techniques for HBM3. - Jinook Jung; Jun-Han Choi; Kyoung-Jun Roh; Jaewoo Park; Won-Mook Lim; Tae-Sung Kim; Han-Ki Jeong; Myoungbo Kwak; Jaeyoun Youn; Jeong-Don Ihm; Changsik Yoo; Youngdon Choi; et al. (IEEE J. Solid State Circuits, 2024)

10.4 A 2- TRX IR-UWB Transceiver with Shared Antennas Supporting Channels 5 to 12 in Compliance with IEEE 802.15.4/4z Standards. - Hyun-Gi Seok; Jae-Keun Lee; Sinyoung Kim; Wonjun Jung; Honggul Han; Junhyeong Kim; Sumin Kang; Chanho Kim; Wonkang Kim; Jongpil Cho; Seungyong Bae; Yanghoon Lee; et al. (ISSCC, 2025)