Algorithms for Combined Inter- and Intra-Task Dynamic Voltage Scaling. - Hyungjung Seo; Jaewon Seo; Taewhan Kim (Comput. J., 2012)

Post-silicon tunable clock buffer allocation based on fast chip yield computation. - Hyungjung Seo; Taewhan Kim (ISQED, 2014)

Synthesis for Power-Aware Clock Spines. - Hyungjung Seo; Juyeon Kim; Minseok Kang; Taewhan Kim 001 (ICCAD, 2015)

Clock skew optimization for maximizing time margin by utilizing flexible flip-flop timing. - Hyungjung Seo; Jeongwoo Heo; Taewhan Kim 001 (ISQED, 2015)

Local Layout Effect-Aware Static Timing Analysis by use of a New Sensitivity-Based Library. - Juyeon Kim; Changho Han; Cheoljun Bae; Yoobeom Kim; Jae Hoon Kim; Hyungjung Seo (ICCAD, 2023)