A 24Gb/s/pin PAM-4 Built Out Tester chip enabling PAM-4 chips test with NRZ interface ATE. - Hyungmin Jin; Jindo Byun; Hyunyoon Cho; Hojun Yoon; Jin-Hee Park; Kyoungsoo Kim; Youngdon Choi; Jung-Hwan Choi; Hyungjong Ko; Sang-Hyun Lee (A-SSCC, 2021)

A 3.2-12.8Gb/s Duty-Cycle Compensating Quadrature Error Corrector for DRAM Interfaces, With Fast Locking and Low Power Characteristics. - Hojun Yoon; Wonjoo Jung; Jaewoo Park; Jindo Byun; Hyungmin Jin; Hyunyoon Cho; Youngmin Kim; Baek-Jin Lim; Young-Chul Cho; Youngdon Choi; Jung-Hwan Choi; Hyungjong Ko; et al. (ESSCIRC, 2021)

A 60-Gb/s/pin single-ended PAM-4 transmitter with timing skew training and low power data encoding in mimicked 10nm class DRAM process. - Joohwan Kim; Junyoung Park; Jindo Byun; Changkyu Seol; Chang Soo Yoon; EunSeok Shin; Hyunyoon Cho; Youngdo Um; Sucheol Lee; Hyungmin Jin; Kwangseob Shin; Hyunsub Norbert Rie; et al. (CICC, 2022)

A 40-Gb/s/pin Low-Voltage POD Single-Ended PAM-4 Transceiver with Timing Calibrated Reset-less Slicer and Bidirectional T-Coil for GDDR7 Application. - Hyunsub Norbert Rie; Chang Soo Yoon; Jindo Byun; Sucheol Lee; Garam Kim; Joohwan Kim; Junyoung Park; Hyunyoon Cho; Youngdo Um; Hyungmin Jin; Kwangseob Shin; Minsu Jung; et al. (VLSI Technology and Circuits, 2022)