Noise generation, coupling, isolation, and EM radiation in high-speed package and PCB. - Joungho Kim; Junso Pak; Jongbae Park; Hyungsoo Kim (ISCAS (6), 2005)

Chip-package hybrid clock distribution network and DLL for low jitter clock delivery. - Daehyun Chung; Chunghyun Ryu; Hyungsoo Kim; Choonheung Lee; Jinhan Kim; Kicheol Bae; Jiheon Yu; Hoi-Jun Yoo; Joungho Kim (IEEE J. Solid State Circuits, 2006)

Co-modeling, Experimental Verification, and Analysis of Chip-Package Hierarchical Power Distribution Network. - Hyunjeong Park; Hyungsoo Kim; Junso Pak; Changwook Yoon; Kyoungchoul Koo; Joungho Kim (IEICE Trans. Electron., 2008)

Efficient transmit antenna selection for correlated MIMO channels. - Hyungsoo Kim; Hyounkuk Kim; Namshik Kim; Hyuncheol Park; Seok Seo; Jin-Kyu Choi (WCNC, 2009)

Energy/carbon management network for IT equipments. - Sungbong Chang; Hyungsoo Kim; Byungdeok Chung; Hyunchul Jung (APNOMS, 2012)

A 1.2V 38nm 2.4Gb/s/pin 2Gb DDR4 SDRAM with bank group and ×4 half-page architecture. - Kibong Koo; Sunghwa Ok; Yonggu Kang; Seungbong Kim; Choungki Song; Hyeyoung Lee; Hyungsoo Kim; Yongmi Kim; Jeonghun Lee; Seunghan Oak; Yosep Lee; Jungyu Lee 002; et al. (ISSCC, 2012)

A 1.2V 23nm 6F2 4Gb DDR3 SDRAM with local-bitline sense amplifier, hybrid LIO sense amplifier and dummy-less array architecture. - Kyu-Nam Lim; Woong-Ju Jang; Hyung-Sik Won; Kang-Yeol Lee; Hyungsoo Kim; Dong-Whee Kim; Mi-Hyun Cho; Seung-Lo Kim; Jong-Ho Kang; Keun-Woo Park; Byung-Tae Jeong (ISSCC, 2012)

Crosstalk-included eye-diagram estimation for high-speed silicon, organic, and glass interposer channels on 2.5D/3D IC. - Sumin Choi; Heegon Kim; Daniel H. Jung; Jonghoon J. Kim; Jaemin Lim; Hyunsuk Lee; Kyungjun Cho; Joungho Kim; Hyungsoo Kim; Yong-Ju Kim; Yunsaing Kim (3DIC, 2015)

A 4.35Gb/s/pin LPDDR4 I/O interface with multi-VOH level, equalization scheme, and duty-training circuit for mobile applications. - Hae-Kang Jung; Jaemo Yang; Jeonghun Lee; Hyeongjun Ko; Hyuk Lee; Taeksang Song; Jongjoo Shim; Sangkwon Lee; Keunsoo Song; Dongkyun Kim; Hyungsoo Kim; Yunsaing Kim (VLSIC, 2015)

23.8 A 1V 7.8mW 15.6Gb/s C-PHY transceiver using tri-level signaling for post-LPDDR4. - Woojun Choi; Taewoong Kim; Jongjoo Shim; Hyungsoo Kim; Gunhee Han; Youngcheol Chae (ISSCC, 2017)

Design and Implementation of Quantum Key Distribution Network Control and Management. - Taesang Choi; Sangsik Yoon; Taeyeon Kim; Hyungsoo Kim (ICTC, 2021)

A 24Gb/s/pin 8Gb GDDR6 with a Half-Rate Daisy-Chain-Based Clocking Architecture and IO Circuitry for Low-Noise Operation. - Kyunghoon Kim; Joo-Hyung Chae; Jaehyeok Yang; Jihyo Kang; Gang-Sik Lee; Sang-Yeon Byeon; Youngtaek Kim; Boram Kim; Dong-Hyun Kim; Yeongmuk Cho; Kangmoo Choi; Hyeongyeol Park; et al. (ISSCC, 2021)

A 1.3-4-GHz Quadrature-Phase Digital DLL Using Sequential Delay Control and Reconfigurable Delay Line. - Hyunsu Park; Jincheol Sim; Yoonjae Choi; Jonghyuck Choi; Youngwook Kwon; Seungwoo Park; Gyutae Park; Jinil Chung; Kyeong-Min Kim; Hae-Kang Jung; Hyungsoo Kim; Junhyun Chun; et al. (IEEE J. Solid State Circuits, 2021)

Quality of Service Evaluation over a 496 km Quantum Key Distribution Network. - Miryeong Park; Kyungwoon Lee; Kanghee Seol; Minsoo Lee; Hyungsoo Kim (SoftCOM, 2022)

A 24-Gb/s/Pin 8-Gb GDDR6 With a Half-Rate Daisy-Chain-Based Clocking Architecture and I/O Circuitry for Low-Noise Operation. - Jihyo Kang; Jaehyeok Yang; Kyunghoon Kim; Joo-Hyung Chae; Gang-Sik Lee; Sang-Yeon Byeon; Boram Kim; Dong-Hyun Kim; Youngtaek Kim; Yeongmuk Cho; Junghwan Ji; Sera Jeong; et al. (IEEE J. Solid State Circuits, 2022)

System Optimization of Data Analytics Platforms using Compute Express Link (CXL) Memory. - Seokhyun Ryu; Sohyun Kim; Jaeyung Jun; Donguk Moon; Kyungsoo Lee; Jungmin Choi; Sunwoong Kim; Hyungsoo Kim; Luke Kim; Won Ha Choi; Moohyeon Nam; Dooyoung Hwang; et al. (BigComp, 2023)