Energy-Efficient Dynamic Comparator with Active Inductor for Receiver of Memory Interfaces. - Jae-Whan Lee; Joo-Hyung Chae; Jihwan Park; Hyunkyu Park 002; Jaekwang Yun; Suhwan Kim 001 (ISLPED, 2018)

A 20Gb/s Dual-Mode PAM4/NRZ Single-Ended Transmitter with RLM Compensation. - Changho Hyun; Hyeongjun Ko; Joo-Hyung Chae; Hyunkyu Park 002; Suhwan Kim 001 (ISCAS, 2019)

A 28-Gb/s/pin PAM-4 Single-Ended Transmitter with High-Linearity and Impedance-Matched Driver and 3-Point ZQ Calibration for Memory Interfaces. - Yong-Un Jeong; Hyunkyu Park 002; Changho Hyun; Suhwan Kim 001 (VLSI Circuits, 2020)

A High-Accuracy and Fast-Correction Quadrature Signal Corrector Using an Adaptive Delay Gain Controller for Memory Interfaces. - Hyunkyu Park 002; Jihwan Park; Jae-Whan Lee; Yong-Un Jeong; Shin-Hyun Jeong; Suhwan Kim 001; Joo-Hyung Chae (ISCAS, 2021)

A 0.64-pJ/Bit 28-Gb/s/Pin High-Linearity Single-Ended PAM-4 Transmitter With an Impedance-Matched Driver and Three-Point ZQ Calibration for Memory Interface. - Yong-Un Jeong; Hyunkyu Park 002; Changho Hyun; Joo-Hyung Chae; Shin-Hyun Jeong; Suhwan Kim 001 (IEEE J. Solid State Circuits, 2021)

A Controller PHY for Managed DRAM Solution With Damping-Resistor-Aided Pulse-Based Feed-Forward Equalizer. - Hyeongjun Ko; Mino Kim; Hyunkyu Park 002; Sangyoon Lee 006; Jaewook Kim; Suhwan Kim 001; Joo-Hyung Chae (IEEE J. Solid State Circuits, 2021)

A 24-Gb/s/pin Single-Ended PAM-4 Receiver With 1-Tap Decision Feedback Equalizer Using Inverter-Based Summer for Memory Interfaces. - Hyunkyu Park 002; Yong-Un Jeong; Suhwan Kim 001 (IEEE Access, 2022)