Sum rates of asynchronous GFDMA and SC-FDMA for 5G uplink. - Woojin Park; Hyun Jong Yang; Hyunmyung Oh (ICT Express, 2015)

Energy-efficient XNOR-free In-Memory BNN Accelerator with Input Distribution Regularization. - Hyungjun Kim; Hyunmyung Oh; Jae-Joon Kim (ICCAD, 2020)

Single RRAM Cell-based In-Memory Accelerator Architecture for Binary Neural Networks. - Hyunmyung Oh; Hyungjun Kim; Nameun Kang; Yulhwa Kim; Jihoon Park; Jae-Joon Kim (AICAS, 2021)

Energy-efficient charge sharing-based 8T2C SRAM in-memory accelerator for binary neural networks in 28nm CMOS. - Hyunmyung Oh; Hyungjun Kim; Daehyun Ahn; Jihoon Park; Yulhwa Kim; Inhwan Lee; Jae-Joon Kim (A-SSCC, 2021)

Mapping Binary ResNets on Computing-In-Memory Hardware with Low-bit ADCs. - Yulhwa Kim; Hyungjun Kim; Jihoon Park; Hyunmyung Oh; Jae-Joon Kim (DATE, 2021)

Maximizing Parallel Activation of Word-Lines in MRAM-Based Binary Neural Network Accelerators. - Daehyun Ahn; Hyunmyung Oh; Hyungjun Kim; Yulhwa Kim; Jae-Joon Kim (IEEE Access, 2021)

TAIM: ternary activation in-memory computing hardware with 6T SRAM array. - Nameun Kang; Hyungjun Kim; Hyunmyung Oh; Jae-Joon Kim (DAC, 2022)

In-Memory Neural Network Accelerator based on eDRAM Cell with Enhanced Retention Time. - Inhwan Lee; Eunhwan Kim; Nameun Kang; Hyunmyung Oh; Jae-Joon Kim (DAC, 2023)

A Capacitive Computing-In-Memory Circuit With Low Input Loading SRAM Bitcell and Adjustable ADC Input Range. - Eunhwan Kim; Hyunmyung Oh; Nameun Kang; Jihoon Park; Jae-Joon Kim (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

A 10T2C Capacitive SRAM-based Computing-In-Memory Macro with Array-Embedded DAC and Shift-and-Add Functions. - Eunhwan Kim; Hyunmyung Oh; Jehun Lee; Jihoon Park; Myeongeun Kwon; Jae-Joon Kim (CICC, 2024)