A Low-Jitter Open-Loop All-Digital Clock Generator with 2 Cycle Lock-Time. - Moo-young Kim; Dongsuk Shin; Hyunsoo Chae; Sunghwa Ok; Chulwoo Kim (CICC, 2007)

A wide-range duty-independent all-digital multiphase clock generator. - Hyunsoo Chae; Sangdon Jung; Chulwoo Kim (ESSCIRC, 2007)

A 7ps-Jitter 0.053mm2 Fast-Lock ADDLL with Wide-Range and High-Resolution All-Digital DCC. - Dongsuk Shin; Janghoon Song; Hyunsoo Chae; Kwan-Weon Kim; Young-Jung Choi; Chulwoo Kim (ISSCC, 2007)

A 7 ps Jitter 0.053 mm2 Fast Lock All-Digital DLL With a Wide Range and High Resolution DCC. - Dongsuk Shin; Janghoon Song; Hyunsoo Chae; Chulwoo Kim (IEEE J. Solid State Circuits, 2009)

A Low-Jitter Open-Loop All-Digital Clock Generator With Two-Cycle Lock-Time. - Moo-young Kim; Dongsuk Shin; Hyunsoo Chae; Chulwoo Kim (IEEE Trans. Very Large Scale Integr. Syst., 2009)