An improved architecture of the mixed mode clock/data recovery for DVD read channel. - Jungeun Lee; Hyunsu Chae; Hanseung Lee; Maxim Konakov; Junghyun Lee; Jeongwon Lee (CICC, 2004)

High speed mixed analog/digital PRML architecture for optical data storage system. - Maxim Konakov; Jae-Wook Lee; Junghyun Lee; Eun-Jin Ryu; Eingseob Cho; Jungeun Lee; Hyunsu Chae; Jeongwon Lee (SoCC, 2004)

A Fast Hopping Frequency Synthesizer for UWB Systems in a CMOS Technology. - Hyunsu Chae; Eun-Chul Park; Choong-Yul Cha; Jungeun Lee; Chun-Deok Suh; Jeongwook Koh; Hanseung Lee; Hoon-Tae Kim (ISWCS, 2005)

Test cost reduction for X-value elimination by scan slice correlation analysis. - Hyunsu Chae; Joon-Sung Yang (DAC, 2018)

A 64Gb/s Downlink and 32Gb/s Uplink NRZ Wireline Transceiver with Supply Regulation, Background Clock Correction and EOM-based Channel Adaptation for Mid-Reach Cellular Mobile Interface in 8nm FinFET. - Soo-Min Lee; Jihoon Lim; Jaehyuk Jang; Hyoungjoong Kim; Kyunghwan Min; Woongki Min; Hyeonji Han; Gyusik Kim; Jaeyoung Kim; Chulho Kim; Sejun Jeon; Jinhoon Park; et al. (ESSCIRC, 2022)

A 4nm 16Gb/s/pin Single-Ended PAM4 Parallel Transceiver with Switching-Jitter Compensation and Transmitter Optimization. - Jahoon Jin; Soo-Min Lee; Kyunghwan Min; Sodam Ju; Jihoon Lim; Hyunsu Chae; Kwonwoo Kang; Yunji Hong; Yeongcheol Jeong; Sang-Ho Kim; Jongwoo Lee; Joonsuk Kim (ISSCC, 2023)

ISOP-Yield: Yield-Aware Stack-Up Optimization for Advanced Package using Machine Learning. - Hyunsu Chae; Keren Zhu 001; Bhyrav Mutnury; Zixuan Jiang; Daniel De Araujo; Douglas Wallace; Douglas Winterberg; Adam R. Klivans; David Z. Pan (ASPDAC, 2024)

PulseRF: Physics Augmented ML Modeling and Synthesis for High-Frequency RFIC Design. - Hyunsu Chae; Hao Yu 022; Sensen Li; David Z. Pan (ICCAD, 2024)

A 4-nm 16-Gb/s/pin Single-Ended PAM-4 Parallel Transceiver With Switching-Jitter Compensation and Transmitter Optimization. - Jahoon Jin; Soo-Min Lee; Kyunghwan Min; Sodam Ju; Jihoon Lim; Jisu Yook; Jihoon Lee; Hyunsu Chae; Kwonwoo Kang; Yunji Hong; Yeongcheol Jeong; Sungsik Park; et al. (IEEE J. Solid State Circuits, 2024)

ISOP+: Machine Learning-Assisted Inverse Stack-Up Optimization for Advanced Package Design. - Hyunsu Chae; Keren Zhu 001; Bhyrav Mutnury; Douglas Wallace; Douglas Winterberg; Daniel De Araujo; Jay Reddy; Adam R. Klivans; David Z. Pan (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

ML-Assisted RF IC Design Enablement: the New Frontier of AI for EDA. - Hyunsu Chae; Song Hang Chai; Taiyun Chi; Sensen Li; David Z. Pan (ASP-DAC, 2025)