Low-cost rapid prototyping of liquid crystal polymer based magnetic microactuators for glaucoma drainage devices. - Hyunsu Park; Simon John; Hyowon Lee 002 (EMBC, 2016)

Development of Flexible Glutamate Biosensor Using Activated Carbon - Pt Microparticle Composite Ink. - Tran Nguyen; Stephanie Lam; Hyunsu Park; Riyi Shi; Hyowon Lee 002 (IEEE SENSORS, 2018)

A Low-Power Post-LPDDR4 Interface Using AC Termination at RX and an Active Inductor at TX. - Jeongsik Yoo; Yeonho Lee 002; Yoonjae Choi; Hyunsu Park; Sanghune Park; Chulwoo Kim (IEEE Trans. Circuits Syst. II Express Briefs, 2018)

A 3-bit/2UI 27Gb/s PAM-3 Single-Ended Transceiver Using One-Tap DFE for Next-Generation Memory Interface. - Hyunsu Park; Junyoung Song; Yeonho Lee 002; Jincheol Sim; Jonghyuck Choi; Chulwoo Kim (ISSCC, 2019)

Effects of Fractal Electrode Geometry in Charge Injection Capacity of TiN Microelectrodes. - Hyunsu Park; Amanda Ruth Maple; Hyowon Lee 002 (EMBC, 2020)

A DLL-Based Quadrature Clock Generator With a 3-Stage Quad Delay Unit Using the Sub-Range Phase Interpolator for Low-Jitter and High-Phase Accuracy DRAM Applications. - Youngbog Yoon; Hyunsu Park; Chulwoo Kim (IEEE Trans. Circuits Syst., 2020)

A 1-3.2 GHz 0.6 mW/GHz Duty-Cycle-Corrector Using Bangbang Duty-Cyle-Detector. - Jincheol Sim; Hyunsu Park; Youngwook Kwon; Seongcheol Kim; Chulwoo Kim (ISCAS, 2021)

A 1.69-pJ/b 14-Gb/s Digital Sub-Sampling CDR With Combined Adaptive Equalizer and Self-Error Corrector. - Yoonjae Choi; Sewook Hwang; Yeonho Lee 002; Hyunsu Park; Jonghyuck Choi; Jincheol Sim; Chulwoo Kim (IEEE Access, 2021)

A 1.3-4-GHz Quadrature-Phase Digital DLL Using Sequential Delay Control and Reconfigurable Delay Line. - Hyunsu Park; Jincheol Sim; Yoonjae Choi; Jonghyuck Choi; Youngwook Kwon; Seungwoo Park; Gyutae Park; Jinil Chung; Kyeong-Min Kim; Hae-Kang Jung; Hyungsoo Kim; Junhyun Chun; et al. (IEEE J. Solid State Circuits, 2021)

30-Gb/s 1.11-pJ/bit Single-Ended PAM-3 Transceiver for High-Speed Memory Links. - Hyunsu Park; Junyoung Song; Jincheol Sim; Yoonjae Choi; Jonghyuck Choi; Jeongsik Yoo; Chulwoo Kim (IEEE J. Solid State Circuits, 2021)

A 0.99-pJ/b 15-Gb/s Counter-Based Adaptive Equalizer Using Single Comparator in 28-nm CMOS. - Yoonjae Choi; Yeonho Lee 002; Hyunsu Park; Jonghyuck Choi; Jincheol Sim; Youngwook Kwon; Chulwoo Kim (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

Experimental Demonstration of RoFSO Transmission Combining WLAN Standard and WDM-FSO over 100m Distance. - Jong-Min Kim; Ju-Hyung Lee 001; Yeongrok Lee; Hong-Seol Cha; Hyunsu Park; Jincheol Sim; Chulwoo Kim; Young-Chai Ko (INFOCOM Workshops, 2022)

A 0.385-pJ/bit 10-Gb/s TIA-Terminated Di-Code Transceiver with Edge-Delayed Equalization, ECC, and Mismatch Calibration for HBM Interfaces. - Hyunsu Park; Yoonjae Choi; Jincheol Sim; Jonghyuck Choi; Youngwook Kwon; Junyoung Song; Chulwoo Kim (ISSCC, 2022)

A 56-Gb/s PAM-4 Receiver Using Time-Based LSB Decoder and S/H Technique for Robustness to Comparator Voltage Variations. - Hyunsu Park; Jincheol Sim; Yoonjae Choi; Jonghyuck Choi; Youngwook Kwon; Chulwoo Kim (IEEE J. Solid State Circuits, 2022)

Analysis of a Multiwire, Multilevel, and Symbol Correlation Combination Scheme. - Jonghyuck Choi; Yoonjae Choi; Hyunsu Park; Jincheol Sim; Youngwook Kwon; Seungwoo Park; Chulwoo Kim (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

A 15 Gb/s Non-Return-to-Zero Transmitter With 1-Tap Pre-Emphasis Feed-Forward Equalizer for Low-Power Ground Terminated Memory Interfaces. - Youngwook Kwon; Hyunsu Park; Yoonjae Choi; Jincheol Sim; Jonghyuck Choi; Seungwoo Park; Chulwoo Kim (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

A 2.4-8 GHz Phase Rotator Delay-Locked Loop Using Cascading Structure for Direct Input-Output Phase Detection. - Hyunsu Park; Jincheol Sim; Yoonjae Choi; Jonghyuck Choi; Youngwook Kwon; Chulwoo Kim (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

A 25 Gb/s Wireline Receiver With Feedforward and Feedback Equalizers at Analog Front-End. - Jincheol Sim; Yeonho Lee 002; Hyunsu Park; Yoonjae Choi; Jonghyuck Choi; Chulwoo Kim (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

A 0.83pJ/b 52Gb/s PAM-4 Baud-Rate CDR with Pattern-Based Phase Detector for Short-Reach Applications. - Seungwoo Park; Yoonjae Choi; Jincheol Sim; Jonghyuck Choi; Hyunsu Park; Youngwook Kwon; Chulwoo Kim (ISSCC, 2023)

A 25-Gb/s Single-Ended PAM-4 Receiver With Time-Windowed LSB Decoder for High-Speed Memory Interfaces. - Yoonjae Choi; Hyunsu Park; Jonghyuck Choi; Jincheol Sim; Youngwook Kwon; Seungwoo Park; Seongcheol Kim; Changmin Sim; Chulwoo Kim (IEEE J. Solid State Circuits, 2023)

A 33-Gb/s/Pin 1.09-pJ/Bit Single-Ended PAM-3 Transceiver With Ground-Referenced Signaling and Time-Domain Decision Technique for Multi-Chip Module Memory Interfaces. - Youngwook Kwon; Hyunsu Park; Yoonjae Choi; Jincheol Sim; Jonghyuck Choi; Seungwoo Park; Kyeong-Min Kim; Changkyu Choi; Hae-Kang Jung; Chulwoo Kim (IEEE J. Solid State Circuits, 2023)

A 15-Gb/s Single-Ended NRZ Receiver Using Self-Referenced Technique With 1-Tap Latched DFE for DRAM Interfaces. - Seongcheol Kim; Jincheol Sim; Hyunsu Park; Yoonjae Choi; Jonghyuck Choi; Chulwoo Kim (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

A 16-Gb/s NRZ Receiver With 0.0019-pJ/bit/dB 1-Tap Charge-Redistribution DFE. - Jonghyuck Choi; Yoonjae Choi; Hyunsu Park; Jincheol Sim; Youngwook Kwon; Seungwoo Park; Seongcheol Kim; Chulwoo Kim (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

PAM-4 Receiver With 1-Tap DFE Using Clocked Comparator Offset Instead of Threshold Voltages for Improved LSB BER Performance. - Jincheol Sim; Hyunsu Park; Yoonjae Choi; Jonghyuck Choi; Youngwook Kwon; Chulwoo Kim (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

A 4-GHz Ring-Oscillator-Based Digital Sub-Sampling PLL With Energy-Efficient Dual-Domain Phase Detector. - Yoonjae Choi; Hyunsu Park; Jonghyuck Choi; Jincheol Sim; Youngwook Kwon; Seungwoo Park; Changmin Sim; Chulwoo Kim (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

13.1 A 35.4Gb/s/pin 16Gb GDDR7 with a Low-Power Clocking Architecture and PAM3 IO Circuitry. - Jaehyeok Yang; Hyeongjun Ko; Kyunghoon Kim; Hyunsu Park; Jihwan Park; Ji-Hyo Kang; Jin-Youp Cha; Seongjin Kim; Youngtaek Kim; Minsoo Park; Gangsik Lee; Keonho Lee; et al. (ISSCC, 2024)

An 11 Gb/s 0.376 pJ/Bit Capacitor-Less Dicode Transceiver With Pattern-Dependent Equalizations TIA Termination for Parallel DRAM Interfaces. - Hyunsu Park; Seung-Myeong Yu; Junyoung Song (IEEE Access, 2024)

Flotation separation of lithium-ion battery electrodes predicted by a long short-term memory network using data from physicochemical kinetic simulations and experiments. - Allan Gomez-Flores; Hyunsu Park; Gilsang Hong; Hyojeong Nam; Juan Gomez-Flores; Seungmin Kang; Graeme W. Heyes; Laurindo de S. Leal Filho; Hyunjung Kim; Jung Mi Lee; Junseop Lee (J. Ind. Inf. Integr., 2024)

A 10-Gb/s Wireline Receiver Using Linear Baud-Rate CDR and Analog Equalizer for Free Space Optical Communication Over 10- and 100-m Distances. - Jincheol Sim; Changmin Sim; Hyunsu Park; Yoonjae Choi; Jonghyuck Choi; Youngwook Kwon; Seungwoo Park; Seongcheol Kim; Jong-Min Kim; Ju-Hyung Lee 001; Young-Chai Ko; Chulwoo Kim (IEEE J. Solid State Circuits, 2024)

A 25-Gb/s Single-Ended PAM-4 Transmitter With iPWM-Based FFE and RLM-Matched Voltage-Mode Driver for High-Speed Memory Interfaces. - Yoonjae Choi; Changmin Sim; Jonghyuck Choi; Jincheol Sim; Hyunsu Park; Youngwook Kwon; Seungwoo Park; Seongcheol Kim; Chulwoo Kim (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)

A 52-Gb/s Low-Power PAM-4 Baud-Rate CDR Using Pattern-Based Phase Detector for Short-Reach Applications. - Seungwoo Park; Yoonjae Choi; Jincheol Sim; Jonghyuck Choi; Hyunsu Park; Youngwook Kwon; Changmin Sim; Seongcheol Kim; Chulwoo Kim (IEEE J. Solid State Circuits, 2025)