A 2.5Gb/s/pin 256Mb GDDR3 SDRAM with Series Pipelined CAS Latency Control and Dual-Loop Digital DLL. - Dong-Uk Lee; Hyun Woo Lee 013; Ki Chang Kwean; Young-Kyoung Choi; Hyong Uk Moon; Seung-Wook Kwack; Shin-Deok Kang; Kwan-Weon Kim; Yong Ju Kim; Young-Jung Choi; Patrick B. Moran; Jin-Hong Ahn; et al. (ISSCC, 2006)

A 0.17-1.4GHz low-jitter all digital DLL with TDC-based DCC using pulse width detection scheme. - Dongsuk Shin; Won-Joo Yun; Hyun-Woo Lee 013; Young-Jung Choi; Suki Kim; Chulwoo Kim (ESSCIRC, 2008)

Multi-Slew-Rate Output Driver and Optimized Impedance-Calibration Circuit for 66nm 3.0Gb/s/pin DRAM Interface. - Dong-Uk Lee; Shin-Deok Kang; Nak-Kyu Park; Hyun Woo Lee 013; Young-Kyoung Choi; Jung-Woo Lee; Seung-Wook Kwack; Hyeong-Ouk Lee; Won-Joo Yun; Sang-Hoon Shin; Kwan-Weon Kim; Young-Jung Choi; et al. (ISSCC, 2008)

A 0.1-to-1.5GHz 4.2mW All-Digital DLL with Dual Duty-Cycle Correction Circuit and Update Gear Circuit for DRAM in 66nm CMOS Technology. - Won-Joo Yun; Hyun Woo Lee 013; Dongsuk Shin; Shin-Deok Kang; Ji-Yeon Yang; Hyeng-Ouk Lee; Dong-Uk Lee; Sujeong Sim; Young-Ju Kim 001; Won-Jun Choi; Keun-Soo Song; Sang-Hoon Shin; et al. (ISSCC, 2008)

A 1.6V 3.3Gb/s GDDR3 DRAM with dual-mode phase- and delay-locked loop using power-noise management with unregulated power supply in 54nm CMOS. - Hyun-Woo Lee 013; Won-Joo Yun; Young-Kyoung Choi; Hyang-Hwa Choi; Jong-Jin Lee; Ki-Han Kim; Shin-Deok Kang; Ji-Yeon Yang; Jae-Suck Kang; Hyeng-Ouk Lee; Dong-Uk Lee; Sujeong Sim; et al. (ISSCC, 2009)

Coverage expandable current type code controlled DCC with TDC-based range selector. - Won-Joo Yun; Hyun-Woo Lee 013; Dongsuk Shin; Young-Jung Choi; Suki Kim (IEICE Electron. Express, 2009)

A 7.7mW/1.0ns/1.35V delay locked loop with racing mode and OA-DCC for DRAM interface. - Hyun-Woo Lee 013; Yong-Hoon Kim; Won-Joo Yun; Eun Young Park; Kang Youl Lee; Jaeil Kim; Kwang Hyun Kim; Jongho Jung; Kyung Whan Kim; Nam Gyu Rye; Kwan-Weon Kim; Jun Hyun Chun; et al. (ISCAS, 2010)

A 1.6V 1.4Gb/s/pin consumer DRAM with self-dynamic voltage-scaling technique in 44nm CMOS technology. - Hyun-Woo Lee 013; Ki-Han Kim; Young-Kyoung Choi; Ju-Hwan Shon; Nak-Kyu Park; Kwan-Weon Kim; Chulwoo Kim; Young-Jung Choi; Byong-Tae Chung (ISSCC, 2011)

A 283.2μW 800Mb/s/pin DLL-based data self-aligner for Through-Silicon Via (TSV) interface. - Hyun-Woo Lee 013; Soo-Bin Lim; Junyoung Song; Jabeom Koo; Dae-Han Kwon; Jong-Ho Kang; Yunsaing Kim; Young-Jung Choi; Kunwoo Park; Byong-Tae Chung; Chulwoo Kim (ISSCC, 2012)

A 1.0-ns/1.0-V Delay-Locked Loop With Racing Mode and Countered CAS Latency Controller for DRAM Interfaces. - Hyun-Woo Lee 013; Hoon Choi; Beom-Ju Shin; Kyung-Hoon Kim; Kyung Whan Kim; Jaeil Kim; Kwang Hyun Kim; Jongho Jung; Jae-Hwan Kim; Eun Young Park; Jong-Sam Kim; Jong-Hwan Kim; et al. (IEEE J. Solid State Circuits, 2012)

A 1.6 V 1.4 Gbp/s/pin Consumer DRAM With Self-Dynamic Voltage Scaling Technique in 44 nm CMOS Technology. - Hyun-Woo Lee 013; Ki-Han Kim; Young-Kyoung Choi; Ju-Hwan Sohn; Nak-Kyu Park; Kwan-Weon Kim; Chulwoo Kim; Young-Jung Choi; Byong-Tae Chung (IEEE J. Solid State Circuits, 2012)

A 7.5Gb/s referenceless transceiver for UHDTV with adaptive equalization and bandwidth scanning technique in 0.13µm CMOS process. - Junyoung Song; Hyun-Woo Lee 013; Sewook Hwang; Inhwa Jung; Chulwoo Kim (ASP-DAC, 2013)

An adaptive-bandwidth PLL for avoiding noise interference and DFE-less fast precharge sampling for over 10Gb/s/pin graphics DRAM interface. - Junyoung Song; Hyun-Woo Lee 013; Soo-Bin Lim; Sewook Hwang; Yunsaing Kim; Young-Jung Choi; Byong-Tae Chung; Chulwoo Kim (ISSCC, 2013)

A 247 µW 800 Mb/s/pin DLL-Based Data Self-Aligner for Through Silicon via (TSV) Interface. - Soo-Bin Lim; Hyun-Woo Lee 013; Junyoung Song; Chulwoo Kim (IEEE J. Solid State Circuits, 2013)

25.3 A 1.35V 5.0Gb/s/pin GDDR5M with 5.4mW standby power and an error-adaptive duty-cycle corrector. - Hyun-Woo Lee 013; Junyoung Song; Sangah Hyun; Seunggeun Baek; Yuri Lim; Jungwan Lee; Minsu Park; Haerang Choi; Changkyu Choi; Jin-Youp Cha; Jaeil Kim; Hoon Choi; et al. (ISSCC, 2014)

A 7.5-Gb/s Referenceless Transceiver With Adaptive Equalization and Bandwidth-Shifting Technique for Ultrahigh-Definition Television in a 0.13- µm CMOS Process. - Junyoung Song; Sewook Hwang; Hyun-Woo Lee 013; Chulwoo Kim (IEEE Trans. Circuits Syst. II Express Briefs, 2014)

Survey and Analysis of Delay-Locked Loops Used in DRAM Interfaces. - Hyun-Woo Lee 013; Chulwoo Kim (IEEE Trans. Very Large Scale Integr. Syst., 2014)

High-Bandwidth Memory Interface - Chulwoo Kim; Hyun-Woo Lee 013; Junyoung Song (Springer, 2014)

17.6 1V 10Gb/s/pin single-ended transceiver with controllable active-inductor-based driver and adaptively calibrated cascade-DFE for post-LPDDR4 interfaces. - Junyoung Song; Hyun-Woo Lee 013; Jayoung Kim; Sewook Hwang; Chulwoo Kim (ISSCC, 2015)

A 10 Gbits/s/pin DFE-Less Graphics DRAM Interface With Adaptive-Bandwidth PLL for Avoiding Noise Interference and CIJ Reduction Technique. - Junyoung Song; Hyun-Woo Lee 013; Sewook Hwang; Chulwoo Kim (IEEE Trans. Very Large Scale Integr. Syst., 2017)

A 1-V 10-Gb/s/pin Single-Ended Transceiver With Controllable Active-Inductor-Based Driver and Adaptively Calibrated Cascaded-Equalizer for Post-LPDDR4 Interfaces. - Junyoung Song; Sewook Hwang; Hyun-Woo Lee 013; Chulwoo Kim (IEEE Trans. Circuits Syst. I Regul. Pap., 2018)