Lateral Acceleration Compensation of a Vehicle based on Roll Angle Estimation. - Kwanghyun Cho; Hyunwoo Son; Seibum B. Choi; Sukchang Kang (CCA, 2010)

A 0.65-to-10.5 Gb/s Reference-Less CDR With Asynchronous Baud-Rate Sampling for Frequency Acquisition and Adaptive Equalization. - Seungnam Choi; Hyunwoo Son; Jongshin Shin; Sang-Hyun Lee; Byungsub Kim; Hong-June Park; Jae-Yoon Sim (IEEE Trans. Circuits Syst. I Regul. Pap., 2016)

5.8 A 9.3nW all-in-one bandgap voltage and current reference circuit. - Youngwoo Ji; Cheonhoo Jeon; Hyunwoo Son; Byungsub Kim; Hong-June Park; Jae-Yoon Sim (ISSCC, 2017)

A Low-Power Wide Dynamic-Range Current Readout Circuit for Ion-Sensitive FET Sensors. - Hyunwoo Son; Hwasuk Cho; Jahyun Koo 001; Youngwoo Ji; Byungsub Kim; Hong-June Park; Jae-Yoon Sim (IEEE Trans. Biomed. Circuits Syst., 2017)

A 9.3 nW all-in-one bandgap voltage and current reference circuit using leakage-based PTAT generation and DIBL characteristic. - Youngwoo Ji; Cheonhoo Jeon; Hyunwoo Son; Byungsub Kim; Hong-June Park; Jae-Yoon Sim (ASP-DAC, 2018)

A low-power wide dynamic-range current readout circuit for biosensors. - Hyunwoo Son; Hwasuk Cho; Jahyun Koo 001; Youngwoo Ji; Byungsub Kim; Hong-June Park; Jae-Yoon Sim (ASP-DAC, 2018)

An 84.6-dB-SNDR and 98.2-dB-SFDR Residue-Integrated SAR ADC for Low-Power Sensor Applications. - Seungnam Choi; Hwan-Seok Ku; Hyunwoo Son; Byungsub Kim; Hong-June Park; Jae-Yoon Sim (IEEE J. Solid State Circuits, 2018)

An On-Chip Learning Neuromorphic Autoencoder With Current-Mode Transposable Memory Read and Virtual Lookup Table. - Hwasuk Cho; Hyunwoo Son; Kihwan Seong; Byungsub Kim; Hong-June Park; Jae-Yoon Sim (IEEE Trans. Biomed. Circuits Syst., 2018)

A Multilayer-Learning Current-Mode Neuromorphic System With Analog-Error Compensation. - Hyunwoo Son; Hwasuk Cho; Jungho Lee; Seongun Bae; Byungsub Kim; Hong-June Park; Jae-Yoon Sim (IEEE Trans. Biomed. Circuits Syst., 2019)

Vehicle Side-Slip Angle Estimation of Ground Vehicles Based on a Lateral Acceleration Compensation. - Kwanghyun Cho; Hyunwoo Son; Yafei Wang 001; Kanghyun Nam; Seibum Choi (IEEE Access, 2020)

A pattern-dependent injection-locked CDR for clock-embedded signaling. - Jaehyeong Hong; Dong Hoon Baek; Hyunwoo Son; Cheolmin Ahn; Byungsub Kim; Hong-June Park; Jae-Yoon Sim (Microelectron. J., 2020)

28.5 A 0.6V/0.9V 26.6-to-119.3µW ΔΣ-Based Bio-Impedance Readout IC with 101.9dB SNR and <0.1Hz 1/f Corner. - Tantan Zhang; Hyunwoo Son; Yuan Gao 011; Jingjing Lan; Chun-Huat Heng (ISSCC, 2021)

A 310-nA Quiescent Current 3-fs-FoM Fully Integrated Capacitorless Time-Domain LDO With Event-Driven Charge Pump and Feedforward Transient Enhancement. - Jianming Zhao; Yuan Gao 011; Tantan Zhang; Hyunwoo Son; Chun-Huat Heng (IEEE J. Solid State Circuits, 2021)

A 127.8TOPS/W Arbitrarily Quantized 1-to-8b Scalable-Precision Accelerator for General-Purpose Deep Learning with Reduction of Storage, Logic and Latency Waste. - Seunghyun Moon; Han-Gyeol Mun; Hyunwoo Son; Jae-Yoon Sim (ISSCC, 2023)

A 28 nm 66.8 TOPS/W Sparsity-Aware Dynamic-Precision Deep-Learning Processor. - Han-Gyeol Mun; Hyunwoo Son; Seunghyun Moon; Jaehyun Park; ByungJun Kim; Jae-Yoon Sim (VLSI Technology and Circuits, 2023)

A 26.6-119.3-μW 101.9-dB SNR Direct Digitization Bio-Impedance Readout IC. - Tan-Tan Zhang; Hyunwoo Son; Jianming Zhao; Chun-Huat Heng; Yuan Gao 011 (IEEE J. Solid State Circuits, 2023)

Multipurpose Deep-Learning Accelerator for Arbitrary Quantization With Reduction of Storage, Logic, and Latency Waste. - Seunghyun Moon; Han-Gyeol Mun; Hyunwoo Son; Jae-Yoon Sim (IEEE J. Solid State Circuits, 2024)

Hybrid Energy Storage Systems, Converter Topologies, Energy Management Systems, and Future Prospects of Green Marine Technology: A Comprehensive Review. - Md. Rubel Sarkar; Yunho Park; Haneul Park; Junghyun Woo; Hyunwoo Son (IEEE Access, 2025)

A 9.6-nW Wake-Up Timer With RC-Referenced Subharmonic Locking Using Dual Leakage-Based Oscillators. - Jahyun Koo 001; Hyunwoo Son; Jae-Yoon Sim (IEEE Trans. Very Large Scale Integr. Syst., 2025)