A 1.2V 12.8GB/s 2Gb mobile Wide-I/O DRAM with 4×128 I/Os using TSV-based stacking. - Jung-Sik Kim; Chi Sung Oh; Hocheol Lee; Donghyuk Lee; Hyong-Ryol Hwang; Sooman Hwang; Byongwook Na; Joungwook Moon; Jin-Guk Kim; Hanna Park; Jang-Woo Ryu; Kiwon Park; et al. (ISSCC, 2011)

A 1.2V 30nm 1.6Gb/s/pin 4Gb LPDDR3 SDRAM with input skew calibration and enhanced control scheme. - Yong-Cheol Bae; Joon-Young Park; Sang Jae Rhee; Seung-Bum Ko; Yonggwon Jeong; Kwang-Sook Noh; Young Hoon Son; Jaeyoun Youn; Yonggyu Chu; Hyunyoon Cho; Mijo Kim; Daesik Yim; et al. (ISSCC, 2012)

A 1.2 V 12.8 GB/s 2 Gb Mobile Wide-I/O DRAM With 4 × 128 I/Os Using TSV Based Stacking. - Jung-Sik Kim; Chi Sung Oh; Hocheol Lee; Donghyuk Lee; Hyong-Ryol Hwang; Sooman Hwang; Byongwook Na; Joungwook Moon; Jin-Guk Kim; Hanna Park; Jang-Woo Ryu; Kiwon Park; et al. (IEEE J. Solid State Circuits, 2012)

Dual-loop 2-step ZQ calibration for dedicated power supply voltage in LPDDR4 SDRAM. - Chang-Kyo Lee; Junha Lee; Kiho Kim; Jin-Seok Heo; Gil-Hoon Cha; Jin-Hyeok Baek; Daesik Moon; Yoon-Joo Eom; Tae-Sung Kim; Hyunyoon Cho; Young Hoon Son; Seonghwan Kim 002; et al. (A-SSCC, 2017)

Defect Analysis and Cost-Effective Resilience Architecture for Future DRAM Devices. - Sang-uhn Cha; Seongil O; Hyunsung Shin; Sangjoon Hwang; Kwang-Il Park; Seong-Jin Jang; Joo-Sun Choi; Gyo-Young Jin; Young Hoon Son; Hyunyoon Cho; Jung Ho Ahn; Nam Sung Kim (HPCA, 2017)

SOUP-N-SALAD: Allocation-Oblivious Access Latency Reduction with Asymmetric DRAM Microarchitectures. - Yuhwan Ro; Hyunyoon Cho; Eojin Lee; Daejin Jung; Young Hoon Son; Jung Ho Ahn; Jae W. Lee (HPCA, 2017)

Understanding power-performance relationship of energy-efficient modern DRAM devices. - Sukhan Lee 002; Yuhwan Ro; Young Hoon Son; Hyunyoon Cho; Nam Sung Kim; Jung Ho Ahn (IISWC, 2017)

SALAD: Achieving Symmetric Access Latency with Asymmetric DRAM Architecture. - Young Hoon Son; Hyunyoon Cho; Yuhwan Ro; Jae W. Lee; Jung Ho Ahn (IEEE Comput. Archit. Lett., 2017)

Leveraging Power-Performance Relationship of Energy-Efficient Modern DRAM Devices. - Sukhan Lee 002; Hyunyoon Cho; Young Hoon Son; Yuhwan Ro; Nam Sung Kim; Jung Ho Ahn (IEEE Access, 2018)

A 7.5Gb/s/pin LPDDR5 SDRAM With WCK Clocking and Non-Target ODT for High Speed and With DVFS, Internal Data Copy, and Deep-Sleep Mode for Low Power. - Kyung-Soo Ha; Chang-Kyo Lee; Dongkeon Lee; Daesik Moon; Jin-Hun Jang; Hyong-Ryol Hwang; Hyung-Joon Chi; Junghwan Park; Seungjun Shin; Dukha Park; Sang-Yun Kim 001; Sukhyun Lim; et al. (ISSCC, 2019)

22.2 An 8.5Gb/s/pin 12Gb-LPDDR5 SDRAM with a Hybrid-Bank Architecture using Skew-Tolerant, Low-Power and Speed-Boosting Techniques in a 2nd generation 10nm DRAM Process. - Hyung-Joon Chi; Chang-Kyo Lee; Junghwan Park; Jin-Seok Heo; Jaehoon Jung; Dongkeon Lee; Dae-Hyun Kim 003; Dukha Park; Kihan Kim; Sang-Yun Kim 001; Jinsol Park; Hyunyoon Cho; et al. (ISSCC, 2020)

A 24Gb/s/pin PAM-4 Built Out Tester chip enabling PAM-4 chips test with NRZ interface ATE. - Hyungmin Jin; Jindo Byun; Hyunyoon Cho; Hojun Yoon; Jin-Hee Park; Kyoungsoo Kim; Youngdon Choi; Jung-Hwan Choi; Hyungjong Ko; Sang-Hyun Lee (A-SSCC, 2021)

A 3.2-12.8Gb/s Duty-Cycle Compensating Quadrature Error Corrector for DRAM Interfaces, With Fast Locking and Low Power Characteristics. - Hojun Yoon; Wonjoo Jung; Jaewoo Park; Jindo Byun; Hyungmin Jin; Hyunyoon Cho; Youngmin Kim; Baek-Jin Lim; Young-Chul Cho; Youngdon Choi; Jung-Hwan Choi; Hyungjong Ko; et al. (ESSCIRC, 2021)

A 60-Gb/s/pin single-ended PAM-4 transmitter with timing skew training and low power data encoding in mimicked 10nm class DRAM process. - Joohwan Kim; Junyoung Park; Jindo Byun; Changkyu Seol; Chang Soo Yoon; EunSeok Shin; Hyunyoon Cho; Youngdo Um; Sucheol Lee; Hyungmin Jin; Kwangseob Shin; Hyunsub Norbert Rie; et al. (CICC, 2022)

A 40-Gb/s/pin Low-Voltage POD Single-Ended PAM-4 Transceiver with Timing Calibrated Reset-less Slicer and Bidirectional T-Coil for GDDR7 Application. - Hyunsub Norbert Rie; Chang Soo Yoon; Jindo Byun; Sucheol Lee; Garam Kim; Joohwan Kim; Junyoung Park; Hyunyoon Cho; Youngdo Um; Hyungmin Jin; Kwangseob Shin; Minsu Jung; et al. (VLSI Technology and Circuits, 2022)