A 3.3 V 1 GHz high speed pipelined Booth multiplier. - Hwang-Cherng Chow; I-Chyn Wey (ISCAS (1), 2002)

A 3.3 V 1 GHz low-latency pipelined Booth multiplier with new Manchester carry-pass adder. - Hwang-Cherng Chow; I-Chyn Wey (ISCAS (5), 2003)

A 2Gb/s high-speed scalable shift-register based on-chip serial communication design for SoC applications. - I-Chyn Wey; Lung-Hao Chang; You-Gang Chen; Shih-Hung Chang; An-Yeu Wu (ISCAS (2), 2005)

A scalable DCO design for portable ADPLL designs. - Chia-Tsun Wu; Wei Wang 252; I-Chyn Wey; An-Yeu Wu (ISCAS (6), 2005)

A portable all-digital pulsewidth control loop for SOC applications. - Wei Wang 252; I-Chyn Wey; Chia-Tsun Wu; An-Yeu Wu (ISCAS, 2006)

A frequency estimation algorithm for ADPLL designs with two-cycle lock-in time. - Chia-Tsun Wu; Wei Wang 252; I-Chyn Wey; An-Yeu Wu (ISCAS, 2006)

Ensemble Dependent Matrix Methodology for Probabilistic-Based Fault-tolerant Nanoscale Circuit Design. - Huifei Rao; Jie Chen 002; Changhong Yu; Woon Tiong Ang; I-Chyn Wey; An-Yeu Wu; Hong Zhao (ISCAS, 2007)

Low-Latency Quasi-Synchronous Transmission Technique for Multiple-Clock-Domain IP Modules. - Jhao-Ji Ye; You-Gang Chen; I-Chyn Wey; An-Yeu Wu (ISCAS, 2007)

Dynamic Channel Flow Control of Networks-on-Chip Systems for High Buffer Efficiency. - Sung-Tze Wu; Chih-Hao Chao; I-Chyn Wey; An-Yeu Wu (SiPS, 2007)

An efficient methodology to evaluate nanoscale circuit fault-tolerance performance based on belief propagation. - Huifei Rao; Jie Chen 002; Vicky H. Zhao; Woon Tiong Ang; I-Chyn Wey; An-Yeu Wu (ISCAS, 2008)

Design and Analysis of Isolated Noise-Tolerant (INT) Technique in Dynamic CMOS Circuits. - I-Chyn Wey; You-Gang Chen; An-Yeu Wu (IEEE Trans. Very Large Scale Integr. Syst., 2008)

Design and Implementation of Cost-Effective Probabilistic-Based Noise-Tolerant VLSI Circuits. - I-Chyn Wey; You-Gang Chen; Changhong Yu; An-Yeu Wu; Jie Chen 002 (IEEE Trans. Circuits Syst. I Regul. Pap., 2009)

Low-Error and Hardware-Efficient Fixed-Width Multiplier by Using the Dual-Group Minor Input Correction Vector to Lower Input Correction Vector Compensation Error. - I-Chyn Wey; Chun-Chien Wang (IEEE Trans. Very Large Scale Integr. Syst., 2012)

Reliable ultra-low-voltage low-power probabilistic-based noise-tolerant latch design. - I-Chyn Wey; Yi-Jung Lan; Chien-Chang Peng (Microelectron. Reliab., 2013)

A wide-range and fast-locking frequency synthesizer for Wimax and WLAN applications. - Chun-Yen Wu; Chi-Nan Chuang; Chao-Chyun Chen; I-Chyn Wey (GCCE, 2014)

Reliable and low error dual modular redundancy FIR filter with wide protection window. - I-Chyn Wey; Chien-Chang Peng; Heng-Jui Chou; Po Tsang Chen (IEICE Electron. Express, 2014)

All digital folded low-area, low-power maximum power point tracking chip for photovoltaic energy conversion system. - I-Chyn Wey; Shu-Hao Kuo (Int. J. Circuit Theory Appl., 2014)

Wide bandwidth and high precision power supply noise detector by using dual peak detection sample and hold circuits. - I-Chyn Wey; Chien-Chang Peng; Hwang-Cherng Chow (Int. J. Circuit Theory Appl., 2014)

Hardware-efficient common-feedback Markov-random-field probabilistic-based noise-tolerant VLSI circuits. - I-Chyn Wey; Ye-Jhih Shen (Integr., 2014)

A low power-delay-product and robust Isolated-DICE based SEU-tolerant latch circuit design. - I-Chyn Wey; Yu-Sheng Yang; Bing-Chen Wu; Chien-Chang Peng (Microelectron. J., 2014)

Dynamic-static hybrid near-threshold-voltage adder design for ultra-low power applications. - Xin-Xiang Lian; I-Chyn Wey; Chien-Chang Peng; Zhi-Qun Cheng (IEICE Electron. Express, 2015)

Robust C-element design for soft-error mitigation. - I-Chyn Wey; Bing-Chen Wu; Chien-Chang Peng; Cihun-Siyong Alex Gong; Changhong Yu (IEICE Electron. Express, 2015)

Noise-tolerant dynamic CMOS circuits design by using true single-phase clock latching technique. - I-Chyn Wey; Chun-Wei Chang; Yu-Cheng Liao; Heng-Jui Chou (Int. J. Circuit Theory Appl., 2015)

Reliable Low-Power Multiplier Design Using Fixed-Width Replica Redundancy Block. - I-Chyn Wey; Chien-Chang Peng; Feng-Yu Liao (IEEE Trans. Very Large Scale Integr. Syst., 2015)

Power management design for lab-on-chip biosensors. - Xiaojian Yu; Kambiz Moez; I-Chyn Wey; Jie Chen 002 (EMBC, 2016)

Fast predictive motion estimation algorithm with adaptive search mode based on motion type classification. - Lili Lin; I-Chyn Wey; Jing-Hua Ding (Signal Image Video Process., 2016)

A Fully Integrated Multistage Cross-Coupled Voltage Multiplier With No Reversion Power Loss in a Standard CMOS Process. - Xiaojian Yu; Kambiz Moez; I-Chyn Wey; Mohamad Sawan; Jie Chen 002 (IEEE Trans. Circuits Syst. II Express Briefs, 2017)

Low-Power Noise-Immune Nanoscale Circuit Design Using Coding-Based Partial MRF Method. - Yan Li; Yufeng Li 003; I-Chyn Wey; Jianhao Hu; Fan Yang 001; Xuan Zeng 001; Xiaoxue Jiang; Jie Chen 002 (IEEE J. Solid State Circuits, 2018)

Parallel Balanced-Bit-Serial Design Technique for Ultra-Low-Voltage Circuits With Energy Saving and Area Efficiency Enhancement. - Bing-Chen Wu; I-Chyn Wey (IEEE Trans. Circuits Syst. I Regul. Pap., 2018)

Soft-Event-Upset and Soft-Event-Transient Tolerant CMOS Circuit Design for Low-Voltage Low-Power Wireless IoT Applications. - I-Chyn Wey; Chun-Han Chen; Si-Zhan Fang; Heng-Jui Chou (ICUFN, 2019)

Improved Low-Power Cost-Effective DCT Implementation Based on Markov Random Field and Stochastic Logic. - Yufeng Li 003; Yan Li; I-Chyn Wey; Deqiang Cheng; Fan Yang 001; Xuan Zeng 001; Jie Chen 002 (IEEE Trans. Circuits Syst. Video Technol., 2020)

Wearable Parkinson's Disease Finger Tapping Quantitative Evaluation Algorithm Combined with Impedance Sensing. - Jhih-Syong Fong; Ya-Hui Chuang; Fu-Sheng Yu; I-Chyn Wey; San-Fu Wang (SNPD, 2021)

Systolic Array Based Convolutional Neural Network Inference on FPGA. - Shi Hui Chua; Tee Hui Teo; Mulat Ayinet Tiruye; I-Chyn Wey (MCSoC, 2022)

High-Performance Asynchronous CNN Accelerator with Early Termination. - Tan Rong Loo; Tee Hui Teo; Mulat Ayinet Tiruye; I-Chyn Wey (MCSoC, 2022)

Complex Human Activities Recognition Based on High Performance 1D CNN Model. - Raman Maurya; Tee Hui Teo; Shi Hui Chua; Hwang-Cherng Chow; I-Chyn Wey (MCSoC, 2022)

A Energy-Efficient Re-configurable Multi-mode Convolution Neuron Network Accelerator. - Huan-Ke Hsu; I-Chyn Wey; Tee Hui Teo (MCSoC, 2023)

Convolutional Neural Networks Inference Accelerator Design using Selective Convolutional Layer. - Tzu-Huan Huang; I-Chyn Wey; Emil Goh; Tee Hui Teo (MCSoC, 2023)

Selective Pruning of Sparsity-Supported Energy-Efficient Accelerator for Convolutional Neural Networks. - Chia-Chi Liu; I-Chyn Wey; Xuezhi Zhang; Tee Hui Teo (MCSoC, 2023)

A Convolutional Neural Network Inference Accelerator Design using Algorithmic Noise-Tolerance Technology. - Shih-Yi Yang; I-Chyn Wey; Huan-Ke Hsu; Tee Hui Teo (MCSoC, 2023)

Implementation of Physics Informed Neural Networks on Edge Device. - Xuezhi Zhang; I-Chyn Wey; Maoyang Xiang; Tee Hui Teo (MCSoC, 2023)

Pre-Computing Batch Normalisation Parameters for Edge Devices on a Binarized Neural Network. - Nicholas Phipps; Jin-Jia Shang; Tee Hui Teo; I-Chyn Wey (Sensors, 2023)

Design and Verification of a New Universal Active Filter Based on the Current Feedback Operational Amplifier and Commercial AD844 Integrated Circuit. - Hua-Pin Chen; I-Chyn Wey; Liang-Yen Chen; Cheng-Yueh Wu; San-Fu Wang (Sensors, 2023)

From English to ASIC: Hardware Implementation with Large Language Model. - Emil Goh; Maoyang Xiang; I-Chyn Wey; Tee Hui Teo (CoRR, 2024)

SF-MMCN: A Low Power Re-configurable Server Flow Convolution Neural Network Accelerator. - Huan-Ke Hsu; I-Chyn Wey; Tee Hui Teo (CoRR, 2024)

An Effective Macro Placement Framework with Reinforcement Learning and Monte Carlo Tree Search. - Jinghao Ding; Wenxin Yu 001; Yuanrui Qi; Zhaoqi Fu; Mengshi Gong; I-Chyn Wey; Jinjia Zhou (ACM Great Lakes Symposium on VLSI, 2025)