GBLD: A Formal Model for Layout Description and Generation. - I-Lun Tseng; Adam Postula (FDL, 2004)

An efficient algorithm for partitioning parameterized polygons into rectangles. - I-Lun Tseng; Adam Postula (ACM Great Lakes Symposium on VLSI, 2006)

Partitioning parameterized 45-degree polygons with constraint programming. - I-Lun Tseng; Adam Postula (ACM Trans. Design Autom. Electr. Syst., 2008)

Estimation of Analog Layout Parasitics with Parameterized Polygons - I-Lun Tseng (2008)

Constraint-Based Dogleg Channel Routing with Via Minimization. - I-Lun Tseng; Huan-Wen Chen; Che-I Lee; Adam Postula (IC-AI, 2010)

Relocatable and resizable SRAM synthesis for via configurable structured ASIC. - Hsin-Hung Liu; Rung-Bin Lin; I-Lun Tseng (ISQED, 2013)

Boolean mask operations on parameterized 45-degree polygons. - Yao-I Tseng; I-Lun Tseng; Adam Postula (MWSCAS, 2013)

Fast partitioning of parameterized 45-degree polygons into parameterized trapezoids. - Yao-I Tseng; I-Lun Tseng; Tsao Hsiao Huang; Adam Postula (NEWCAS, 2013)

A parallel dual-scanline algorithm for partitioning parameterized 45-degree polygons. - Yao-Lin Chang; I-Lun Tseng (ACM Trans. Design Autom. Electr. Syst., 2013)

An Automated System for Checking Lithography Friendliness of Standard Cells. - I-Lun Tseng; Yongfu Li 003; Valerio Perez; Vikas Tripathi; Zhao Chuan Lee; Yoong Seang Jonathan Ong (APCCAS, 2018)

Identifying Lithography Weak-Points of Standard Cells with Partial Pattern Matching. - Yongfu Li 003; I-Lun Tseng; Zhao Chuan Lee; Valerio Perez; Vikas Tripathi; Yoong Seang Jonathan Ong (ISVLSI, 2018)

In Design DFM Rule Scoring and Fixing Method using ICV. - Vikas Tripathi; Yongfu Li 003; Zhao Chuan Lee; I-Lun Tseng; Jason Khaw; Jonathan Ong (CoRR, 2018)

Advanced In-Design Auto-Fixing Flow for Cell Abutment Pattern Matching Weakpoints. - Yongfu Li 003; Valerio Perez; I-Lun Tseng; Zhao Chuan Lee; Vikas Tripathi; Jason Khaw; Yoong Seang Jonathan Ong (CoRR, 2018)

Creation and Fixing of Lithography Hotspots with Synopsys Tools. - I-Lun Tseng; Valerio Perez; Yongfu Li 003; Zhao Chuan Lee; Vikas Tripathi; Yoong Seang Jonathan Ong (CoRR, 2018)

Context-Aware DFM Rule Analysis and Scoring Using Machine Learning. - Vikas Tripathi; Valerio Perez; Yongfu Li 003; Zhao Chuan Lee; I-Lun Tseng; Jonathan Ong (CoRR, 2018)

A System for Standard Cell Routability Checking and Placement Routability Improvements. - I-Lun Tseng; Zhao Chuan Lee; Vikas Tripathi; Chun Ming Tommy Yip; Zhinan Chen; Jonathan Ong (APCCAS, 2019)

Flexible chip placement via reinforcement learning: late breaking results. - Fu-Chieh Chang 001; Yu-Wei Tseng; Ya-Wen Yu; Ssu-Rui Lee; Alexandru Cioba; I-Lun Tseng; Da-Shan Shiu; Jhih-Wei Hsu; Cheng-Yuan Wang; Chien-Yi Yang; Ren-Chu Wang; Yao-Wen Chang; et al. (DAC, 2022)

Flexible Multiple-Objective Reinforcement Learning for Chip Placement. - Fu-Chieh Chang 001; Yu-Wei Tseng; Ya-Wen Yu; Ssu-Rui Lee; Alexandru Cioba; I-Lun Tseng; Da-Shan Shiu; Jhih-Wei Hsu; Cheng-Yuan Wang; Chien-Yi Yang; Ren-Chu Wang; Yao-Wen Chang; et al. (CoRR, 2022)

Pragmatic EDA Flow Runtime Prediction with Machine Learning and Automatic Outlier Removal. - I-Lun Tseng (APCCAS, 2024)

Challenges in Floorplanning and Macro Placement for Modern SoCs. - I-Lun Tseng (ISPD, 2024)