Simultaneous Routing and Buffer Insertion with Restrictions on Buffer Locations. - Hai Zhou 001; D. F. Wong 001; I-Min Liu; Adnan Aziz (DAC, 1999)

An Efficient Buffer Insertion Algorithm for Large Networks Based on Lagrangian Relaxation. - I-Min Liu; Adnan Aziz; D. F. Wong 001; Hai Zhou 001 (ICCD, 1999)

Meeting Delay Constraints in DSM by Minimal Repeater Insertion. - I-Min Liu; Adnan Aziz; D. F. Wong 001 (DATE, 2000)

Delay Constrained Optimization by Simultaneous Fanout Tree Construction, Buffer Insertion/Sizing and Gate Sizing. - I-Min Liu; Adnan Aziz (ICCD, 2000)

Zero-skew clock tree construction by simultaneous routing, wire sizing and buffer insertion. - I-Min Liu; Tan-Li Chou; Adnan Aziz; D. F. Wong 001 (ISPD, 2000)

Simultaneous routing and buffer insertion with restrictions onbuffer locations. - Hai Zhou 001; Martin D. F. Wong; I-Min Liu; Adnan Aziz (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000)

Integrated power supply planning and floorplanning. - I-Min Liu; Hung-Ming Chen; Tan-Li Chou; Adnan Aziz; D. F. Wong 001 (ASP-DAC, 2001)

A Polynomial Time Optimal Diode Insertion/Routing Algorithm for Fixing Antenna Problem. - Li-Da Huang; Xiaoping Tang; Hua Xiang 001; D. F. Wong 001; I-Min Liu (DATE, 2002)

Floorplanning with power supply noise avoidance. - Hung-Ming Chen; Li-Da Huang; I-Min Liu; Minghorng Lai; D. F. Wong 001 (ASP-DAC, 2003)

I/O Clustering in Design Cost and Performance Optimization for Flip-Chip Design. - Hung-Ming Chen; I-Min Liu; Martin D. F. Wong; Muzhou Shao; Li-Da Huang (ICCD, 2004)

A polynomial time-optimal diode insertion/routing algorithm for fixing antenna problem [IC layout]. - Li-Da Huang; Xiaoping Tang; Hua Xiang 001; Martin D. F. Wong; I-Min Liu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004)

Post-placement voltage island generation under performance requirement. - Huaizhi Wu; I-Min Liu; Martin D. F. Wong; Yusu Wang 001 (ICCAD, 2005)

Wire Planning with Bounded Over-the-Block Wires. - Hua Xiang 001; I-Min Liu; Martin D. F. Wong (ISQED, 2005)

Simultaneous power supply planning and noise avoidance in floorplan design. - Hung-Ming Chen; Li-Da Huang; I-Min Liu; Martin D. F. Wong (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005)

Timing-constrained and voltage-island-aware voltage assignment. - Huaizhi Wu; Martin D. F. Wong; I-Min Liu (DAC, 2006)

I/O Clustering in Design Cost and Performance Optimization for Flip-Chip Design. - Hung-Ming Chen; I-Min Liu; Martin D. F. Wong (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006)

Placement-Proximity-Based Voltage Island Grouping Under Performance Requirement. - Huaizhi Wu; Martin D. F. Wong; I-Min Liu; Yusu Wang 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007)

Technology mapping with crosstalk noise avoidance. - Fang-Yu Fan; Hung-Ming Chen; I-Min Liu (ASP-DAC, 2010)